Maxim-integrated 73M1866B/73M1966B Implementers Guide Manual do Utilizador descarregar pdf (Página 10)

73M1866B/73M1966B Implementer’s Guide UG_1x66B_016

10 Rev. 1.3

3.2 Line-Side Device (73M1916) Configuration

The Line-side device setup includes the following procedures:

1. Barrier Synchronization Recovery

2. Receiver DC Offset Calibration

3. Initial Line State Configuration

3.2.1 Barrier Synchronization Recovery

Before the Line-side device can be initialized, the barrier must be in sync and error free. The barrier is

designed to power up the line-side device and come into sync automatically upon PLL lock. The user

should check that the device indicates barrier sync before proceeding with line-side initialization.

The following registers control the Barrier Sync procedure.

0x03 GPIO7 GPIO6 GPIO5 PCLKDT RGMON DET SYNL RGDT

Write X X X X X X ? X

0x05 ENGPIO7 ENGPIO6 ENGPIO5 ENPCLKDT ENAPOL ENDET ENSYNL ENRGDT

Write X X X X X X 1 X

0x0D

LOKDET

SLHS

Res

RSTLSBI

Res

Read ? ? X X 1/0 X X X

0x0F

ENFEH

PWDN

SLEEP

Res

Write X X 1/0 X X X X X

0x23

PCMEN

MASTER

PCODE3

PCODE2

PCODE1

PCODE0

LIN

LAW

Write X 1/0 0 0 0 0 X X

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 28 29

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Maxim-integrated 73M1866B/73M1966B Implementers Guide Manual do Utilizador Página 10