Maxim-integrated DS4830A Optical Microcontroller Manual do Utilizador

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circui

DS4830A User’s Guide 10 26.5 – Device Number and I2C Bootloader Address Disable ...

DS4830A User’s Guide 100 11.1.8 – Receiving Data The I2C Slave Controller enters data reception mode after receiving a matching slave address w

DS4830A User’s Guide 101 Figure 11-5: Slave I2C Clock Stretching Normally when the I2C slave controller is receiving data, the value of I2CAC

DS4830A User’s Guide 102 11.1.10 – SMBus Timeout The I2C slave controller can also be used for SMBus or PMBus™ communication. To maintain SMBus

DS4830A User’s Guide 103 11.2 – I2C Slave Controller Register Description Following are the registers that are used to control the I2C Slave In

DS4830A User’s Guide 104 11.2.2 – I2C Slave Status Register (I2CST_S) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I2CBUS I2CBUSY - - - I2CS

DS4830A User’s Guide 105 11.2.3 – I2C Slave Interrupt Enable Register (I2CIE_S) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - - - - I2C

DS4830A User’s Guide 106 11.2.4 – I2C Slave Status2 Register (I2CST2_S) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - - - - - - - - I2C

DS4830A User’s Guide 107 11.2.6 – I2C Slave Address Registers (I2CSLA_S, I2CSLA2_S, I2CSLA3_S and I2CSLA4_S) I2CSLA_S Bit 15 14 13 12 11 10 9

DS4830A User’s Guide 108 11.2.8 – Memory Map Address Register (MADDR) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - ROLLOVR - PAGE[2:0]

DS4830A User’s Guide 109 11.2.12 – Current Slave Address Register (CUR_SLA) Bit 7 6 5 4 3 2 1 0 Name MADDR_EN14 MADDR_EN3 MADDR_EN2 MADDR_EN1

DS4830A User’s Guide 11 SECTION 1 – OVERVIEW The DS4830A optical microcontroller is a low-power, 16-bit microcontroller with a unique periphera

DS4830A User’s Guide 110 11.2.15 – I2C TX Page Interrupt Enable Register (I2CTXFIE) Bit 7 6 5 4 3 2 1 0 Name TXPG_EN - - - - - THSH - Reset 0

DS4830A User’s Guide 111 SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI) The DS4830A provides two independent Serial Peripheral Interfaces (SPI

DS4830A User’s Guide 112 controls whether the active or inactive clock edge is used to latch the data. When CKPHA is set to 1, data is sampled

DS4830A User’s Guide 113 12.1.2 – SPI Character Lengths To flexibly accommodate different SPI transfer data lengths, the character length for a

DS4830A User’s Guide 114 12.2.3 – Write Collision While Busy A write collision occurs if an attempt to write the SPIB data buffer is made durin

DS4830A User’s Guide 115 master’s SPI Clock SFR. The SPI transfer format is selected by the master device using two bits SPI Clock Polarity (CK

DS4830A User’s Guide 116 12.4.3 – SPI Master Register Descriptions SPI Master Module has four SFR registers. These are SPICN_M, SPICF_M, SPICK_

DS4830A User’s Guide 117 12.4.3.2 – SPI Configuration Register (SPICF_M) Bit 7 6 5 4 3 2 1 0 Name ESPII SAS - - - CHR CKPHA CKPOL Reset 0 0 0

DS4830A User’s Guide 118 12.5 – SPI Slave The DS4830A has the following SPI interface signals. FUNCTIONAL NAME EXTERNAL PIN NAME SSPIDO: Outpu

DS4830A User’s Guide 119 12.5.4 – SPI Slave Register Descriptions SPI Slave Module has four SFR registers. These are SPICN_S, SPICF_S, SPICK_S

DS4830A User’s Guide 12 Figure 1-1: DS4830A Block Diagram This document is provided as a supplement to the DS4830A IC data sheet. This user’

DS4830A User’s Guide 120 12.5.4.2 – SPI Configuration Register (SPICF_S) Bit 7 6 5 4 3 2 1 0 Name ESPII SAS - - - CHR CKPHA CKPOL Reset 0 0 0

DS4830A User’s Guide 121 SECTION 13 – 3-WIRE The DS4830A has proprietary 3-Wire master interface for communication with MAXIM 3-wire laser dr

DS4830A User’s Guide 122 13.1.1.1 – Write Mode (RWN=0) The 3-Wire master generates 16 clock cycles on MCL pin. It outputs 16-bits (MSB first DA

DS4830A User’s Guide 123 13.2 – 3-Wire Register Descriptions The 3-Wire interface is controlled by two SFR registers. These are the 3-Wire Con

DS4830A User’s Guide 124 SECTION 14 – PWM The DS4830A provides 10 independent PWM output pins that can be used to create DC-DC power supply c

DS4830A User’s Guide 125 PWMCN.REG_SEL = 00bPWMCN.PWM_SEL =n PWMCN.REG_SEL = 01bPWMCN.PWM_SEL =n PWMCN.REG_SEL = 1xbPWMCN.PWM_SEL =n DCYC0 (Ch0

DS4830A User’s Guide 126 14.2 – Individual PWM Channel Operation Note1: PWM Compare value and PWM Internal Counter are DS4830A internal registe

DS4830A User’s Guide 127 PWM Output High Time128 CyclesPWM Output Low Time384 CyclesPWM Frame = 512 Cycles9-bit PWM Operation in Normal Mode

DS4830A User’s Guide 128 Table 14-2: Number of Slots for Each Resolution RES_SEL[3:0] Resolution PS[1:0]= 00 PS[1:0]= 01 PS[1:0]= 10 PS[1:0]=

DS4830A User’s Guide 129 111Cycles17 Cycles1-Slot = 128 Cycles112Cycles111Cycles17 Cycles16 CyclesPWM OutputLow TimePWM Frame = 1024 Cycles10-b

DS4830A User’s Guide 13 SECTION 2 – ARCHITECTURE The DS4830A contains a low-cost, high-performance microcontroller with flash memory. It is s

DS4830A User’s Guide 130 See Tables 14-4a, 14-4b, and 14-4c for slot frequencies at various resolutions and pulse-spreading options with the di

DS4830A User’s Guide 131 Table 14-4c: Slot Frequencies for Various Resolution and Pulse Spreading with External Clock = 128MHz Source = Extern

DS4830A User’s Guide 132 Programmed Delay. Max 8 Bits (256 clock cycles),for 10 bits of Resolution & 4-slot pulse spreadingSource Clock Fi

DS4830A User’s Guide 133 14.3.1 – PWM Control Register (PWMCN) The PWMCN register is used to setup and start the PWM Output. To avoid undesire

DS4830A User’s Guide 134 14.3.2 – PWM Data Register (PWMDATA) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PWMDATA[15:0] Reset 0 0 0 0 0 0 0

DS4830A User’s Guide 135 14.3.2.2 – Local Register PWMCFGn (through PWMDATA [15:0] Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name INV - ALT_ LO

DS4830A User’s Guide 136 14.3.2.3 – Local Register PWMDLYn PWMCN REG_SEL = 1xb PWMDATA[15:0]  PWMDLY[15:0] BIT NAME DESCRIPTION 15:0 PWMDLYn[1

DS4830A User’s Guide 137 14.4 – PWM Output Code Examples 14.4.1 – 9-Bit PWM Output and Pulse Spreading (PS[1:0]= 11, 1-Slot) with Core Clock C

DS4830A User’s Guide 138 SECTION 15 – GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS 15.1 – Overview The DS4830A provides general-purpose input/

DS4830A User’s Guide 139 Table 15-1: GPIO Pins and Multiplexed Functions Port Index Pin Name Pin No. Default Function Special Function-1 Specia

DS4830A User’s Guide 14 done automatically by the assembler and requires one additional execution cycle. So, while most instructions execute i

DS4830A User’s Guide 140 programming flexibility for any application. The associated registers and their module addresses are listed in Table 1

DS4830A User’s Guide 141 15.2 – GPIO Port Register Descriptions The DS4830A has 4 ports P0, P1, P2 and P6. Each port has 8 pins (exception is P

DS4830A User’s Guide 142 15.2.5 – GPIO Port External Interrupt Flag Register (EIF0, EIF1, EIF2, and EIF6) Bit # 7 6 5 4 3 2 1 0 Name IFPp_7 IF

DS4830A User’s Guide 143 SECTION 16 – GENERAL-PURPOSE TIMERS The DS4830A has two identical 16-bit general-purpose timers. Each timer has the fo

DS4830A User’s Guide 144 interrupt if enabled. When the match occurs, the timer reloads the GTV register with 0x0000 at the next timer clock. I

DS4830A User’s Guide 145 16.2 – Timer Register Descriptions Each General Timer module has three independent SFR registers. These are GTCN, GT

DS4830A User’s Guide 146 16.2.2 – General Timer Value Register (GTV1 and GTV2) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name GTV(1,2) Reset 0

DS4830A User’s Guide 147 SECTION 17 – SUPPLY VOLTAGE MONITOR (SVM) The DS4830A provides feature to allow monitoring its power supply. The Suppl

DS4830A User’s Guide 148 SECTION 18 – HARDWARE MULTIPLIER MODULE The hardware multiplier module can be used by the DS4830A to support high-spee

DS4830A User’s Guide 149 via the MCNT register bits, loading the prescribed number of operands triggers the respective multiply, multiply-accum

DS4830A User’s Guide 15 the source data will be equal to the prefix data as the upper 8 bits and 00h as the lower 8 bits. If the source is from

DS4830A User’s Guide 150 The specified hardware multiplier operation begins when the final operand(s) is loaded and will complete in a single

DS4830A User’s Guide 151 18.5 – Hardware Multiplier Peripheral Registers The hardware multiplier registers are detailed below. Addresses of reg

DS4830A User’s Guide 152 18.5.1 – Multiplier Control Register (MCNT) Bit 7 6 5 4 3 2 1 0 Name OF MCW CLD SQU OPCS MSUB MMAC SUS Reset 0 0 0 0 0

DS4830A User’s Guide 153 18.5.2 – Multiplier Operand A Register (MA) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name MA[15:0] Reset 0 0 0 0 0 0

DS4830A User’s Guide 154 18.5.9 – MAC Select Register (MACSEL) Bit 7 6 5 4 3 2 1 0 Name - - - - - - - MACRSEL Reset 0 0 0 0 0 0 0 0 Access r r

DS4830A User’s Guide 155 18.6 – Hardware Multiplier Examples The following are code examples of multiplier operations. ;Unsigned Multiply 16-b

DS4830A User’s Guide 156 SECTION 19 – WATCHDOG TIMER 19.1 - Overview The Watchdog Timer is a user programmable clock counter that can serve as

DS4830A User’s Guide 157 Table 19-1: Watchdog Operating States EWT EWDI WDIF ACTIONS x X 0 No interrupt has occurred. 0 0 x Watchdog disable, c

DS4830A User’s Guide 158 Table 19-2: Watchdog Timer Control Register Bits (WDCN) Bit 7 6 5 4 3 2 1 0 Name POR EWDI WD1 WD0 WDIF WTRF EWT RWT Re

DS4830A User’s Guide 159 SECTION 20 – TEST ACCESS PORT (TAP) The DS4830A incorporates a Test Access Port (TAP) and TAP controller for communi

DS4830A User’s Guide 16 2.3.4 – Stack Memory A 16-bit, 32-level on-chip stack provides storage for program return addresses and temporary stora

DS4830A User’s Guide 160 20.1 – TAP Controller The TAP controller is a synchronous state machine that responds to changes at the TMS and TCK si

DS4830A User’s Guide 161 20.2 – TAP State Control The TAP provides an independent serial channel to communicate synchronously with the host sy

DS4830A User’s Guide 162 Table 20-3: Instruction Register (IR2:0) Encodings IR2:0 INSTRUCTION FUNCTION SERIAL DATA SHIFT REGISTER SELECTION 000

DS4830A User’s Guide 163 commands and data can be exchanged between the host and the DS4830A by operating in the data register portion of the s

DS4830A User’s Guide 164 Run-Test/IdleSelect-DR-ScanCapture-DRShift-DRExit1-DRPause-DRExit2-DRShift-DRUpdate-DRSelect-IR-ScanExit1-DRRun-Test/I

DS4830A User’s Guide 165 SECTION 21 – IN-CIRCUIT DEBUG MODE The DS4830A is equipped with embedded debug hardware and embedded ROM firmware d

DS4830A User’s Guide 166 TDI TDO9090X X s1 s0Host Command / Data Input StatusDS4830ADS4830A Data Output Figure 21-2: 10-Bit Word Format Table

DS4830A User’s Guide 167 Table 21-2: Background Mode Commands OPCODE COMMAND OPERATION 0000-0000 No Operation No operation. (Default state for

DS4830A User’s Guide 168 21.1.1.1 – Breakpoint 0 Register (BP0) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name BP0[15:0] Reset 1 1 1 1 1 1 1 1

DS4830A User’s Guide 169 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - - - - - r.4 r.3 r.2 r.1 r.0 M.3 M.2 M.1 M.0 Reset 1 1 1 1 1 1 1

DS4830A User’s Guide 17 2.4.2 – Program Memory Mapping The DS4830A’s mapping of the three memory segments (flash, SRAM, and utility ROM) as pro

DS4830A User’s Guide 170 21.2 – Debug Mode There are two ways to enter the Debug Mode from Background Mode: 1. Issuance of the Debug command

DS4830A User’s Guide 171 provide an indication of completion to the host, while others (e.g., Read Register Map) need to supply multiple bytes

DS4830A User’s Guide 172 OPCODE COMMAND OPERATION 0010-0101 Write data memory Write data to a selected data memory location. This command requ

DS4830A User’s Guide 173 Table 21-4: Output from Read Register Map Command WORD REGISTER WORD REGISTER WORD REGISTER WORD REGISTER WORD REG

DS4830A User’s Guide 174 21.2.4 – Return To terminate the debug mode and return the debug engine to background mode, the host must issue a Retu

DS4830A User’s Guide 175 21.3 – In-Circuit Debug Peripheral Registers The following peripheral registers are used to control the in-circuit de

DS4830A User’s Guide 176 21.3.3 – In-Circuit Debug Control Register (ICDC, M2[1Ah]) Bit 7 6 5 4 3 2 1 0 Name DME - REGE - CMD3 CMD2 CMD1 CMD0

DS4830A User’s Guide 177 21.3.4 – In-Circuit Debug Flag Register (ICDF, M2[1Bh]) Bit 7 6 5 4 3 2 1 0 Name - - - - PSS1 PSS0 JTAG_SPE TXC Reset

DS4830A User’s Guide 178 21.3.7 – In-Circuit Debug Data Register (ICDD, M2[1Eh]) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name ICDD[15:0] Res

DS4830A User’s Guide 179 SECTION 22 – IN-SYSTEM PROGRAMMING The DS4830A contains an internal bootstrap loader utilizing the JTAG or I2C interfa

DS4830A User’s Guide 18 pointer. If the data pointer is used as destination, the core performs a store operation that writes data to the memor

DS4830A User’s Guide 180 22.1.1 – Password Protection The DS4830A uses a password to protect the contents of the program memory from simple acc

DS4830A User’s Guide 181 Table 22-2: JTAG Bootloader Status Bits BITS 1:0 STATUS CONDITION 00 Reserved Invalid condition. 01 Reserved Invalid

DS4830A User’s Guide 182 22.2 – Bootloader Operation Once in bootloader mode, the JTAG and I2C interfaces both use the same commands. How thes

DS4830A User’s Guide 183 22.2.2 – I2C Bootloader Protocol After entering the I2C bootloader, all I2C communication takes place on the default I

DS4830A User’s Guide 184 22.3 – Bootloader Commands Commands for the DS4830A loader are grouped into families. All bootloader commands begin

DS4830A User’s Guide 185 22.3.4 – Command 03h – Password Match Byte 1 Bytes 2 to 33 Byte 34 Byte 35 Command Data In NOP Return Input 03h 32-B

DS4830A User’s Guide 186 22.3.6 – Command 05h – Get Supported Commands Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Command NOP Data Out

DS4830A User’s Guide 187 22.3.11 – Command 10h – Load Code Byte 1 Byte 2 Byte 3 Byte 4 (Length) Bytes Byte Length+5 Byte Length+6 Command Da

DS4830A User’s Guide 188 22.3.14 – Command 21h – Dump Data Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 5 Byte 6 Length Bytes Byte Length+7 Comma

DS4830A User’s Guide 189 22.3.17 – Command 40h – Verify Code Byte 1 Byte 2 Byte 3 Byte 4 (Length) Bytes Byte Length+5 Byte Length+6 Command

DS4830A User’s Guide 19 2.4.4.1 – Memory Map When Executing from Flash Memory When executing from the flash memory: • Read and write operation

DS4830A User’s Guide 190 SECTION 23 – PROGRAMMING The following section provides a programming overview of the DS4830A. For full details on th

DS4830A User’s Guide 191 23.3 – Reading and Writing Registers All functions in the DS4830A are accessed through registers, either directly or i

DS4830A User’s Guide 192 move GR, LC[0] ; move LC[0] to the GR register move IC, GRH ; copy the high byt

DS4830A User’s Guide 193 Register bits may be set or cleared individually using the MOVE instruction as follows. move IGE, #1

DS4830A User’s Guide 194 • MOVE Acc, src (Copy data from source to active accumulator) • MOVE dst, Acc (Copy data from active accumulator

DS4830A User’s Guide 195 23.5.3 – ALU Operations Using the Active Accumulator and a Source The following arithmetic and logical operations can

DS4830A User’s Guide 196 Since the Sign flag is a dynamic reflection of the high bit of the active accumulator, any instruction that changes th

DS4830A User’s Guide 197 • XOR Acc.<b> (Carry = Carry XOR selected active accumulator bit) • JUMP C, src (Jump if Carry flag

DS4830A User’s Guide 198 23.7.3 – Conditional Jumps Conditional jumps transfer program execution based on the value of one of the status flags

DS4830A User’s Guide 199 If opting to preload the loop address to an internal 16-bit register, the most time and code efficient means is b

DS4830A User’s Guide 2 Contents SECTION 1 – OVERVIEW ...

DS4830A User’s Guide 20 2.4.4.2 – Memory Map When Executing from Utility ROM When executing from the utility ROM: • Read and write operations

DS4830A User’s Guide 200 ... (interrupt servicing code) ... pop IMR ; restore previous interrupt mask ret

DS4830A User’s Guide 201 Since the stack is 16 bits wide, it is possible to store two 8-bit register values on it in a single location. This al

DS4830A User’s Guide 202 select bits (SDPS1:0; DPC.1:0), or implicitly by writing to the DP[n], BP or OFFS registers. Any indirect memory writ

DS4830A User’s Guide 203 SECTION 24 – INSTRUCTION SET Table 24-1. Instruction Set Summary MNEMONIC DESCRIPTION 16-BIT INSTRUCTION WORD STATUS

DS4830A User’s Guide 204 Note 4: Any index represented by <b> or found inside [ ] brackets is considered variable, but required. Note 5:

DS4830A User’s Guide 205 AND src Logical AND Description: Performs a logical-AND between the active

DS4830A User’s Guide 206 {L/S}CALL src {Long/Short} Call to Subroutine Description: Performs a

DS4830A User’s Guide 207 CMP src Compare Accumulator Description: Compare for equality between the active accumulator

DS4830A User’s Guide 208 {L/S}DJNZ LC[n], src Decrement Counter, {Long/Short} Jump Not Zero Description:

DS4830A User’s Guide 209 {L/S} JUMP src Unconditional {Long/Short} Jump Description: Performs an un

DS4830A User’s Guide 21 2.4.4.3 – Memory Map When Executing from SRAM When executing from the SRAM: • The utility ROM can be read as data, sta

DS4830A User’s Guide 210 {L/S} JUMP C / {L/S} JUMP NC, src Conditional {Long/Short} Jump on S

DS4830A User’s Guide 211 JUMP NZ Operation: Z=0: IP  IP + src (relative) –or— src (absolute) Z=1: IP  IP + 1 Encoding: 15

DS4830A User’s Guide 212 MOVE dst, src Move Data Description: Moves data from a specif

DS4830A User’s Guide 213 MOVE dst, src (continued) Destination Specifier Codesdst dst Bit En

DS4830A User’s Guide 214 Example(s): MOVE A[0], A[3] ; A[0]  A[3] MOVE DP[0], #110h ; DP[0]  #0110h (PFX[

DS4830A User’s Guide 215 MOVE C, Acc.<b> Move Accumulator Bit to Carry Flag Description: Replaces the Carry (C) status flag with the

DS4830A User’s Guide 216 MOVE C, #1 Set Carry Flag Description: Sets the Carry (C) processor status flag.

DS4830A User’s Guide 217 NEG Negate Accumulator Description: Performs a negation (two’s complement) of the a

DS4830A User’s Guide 218 POP dst Pop Word from the Stack Description: Pops a single word from the stack (@SP) to the specified dst and decre

DS4830A User’s Guide 219 PUSH src Push Word to the Stack Description: Increments the stack pointer (SP)

DS4830A User’s Guide 22 2.5 – Data Alignment To support merged program and data memory operation while maintaining efficient memory space usage

DS4830A User’s Guide 220 RET C / RET NC Conditional Return on Status Flag RET Z / RET NZ RET S Descript

DS4830A User’s Guide 221 RETI Return from Interrupt Description: RETI pops a single word from the s

DS4830A User’s Guide 222 RETI Z Operation: Z=1: IP  @SP-- INS 0 Z=0: IP  IP + 1 Encoding: 15

DS4830A User’s Guide 223 RL / RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumul

DS4830A User’s Guide 224 RR / RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the acti

DS4830A User’s Guide 225 SLA / SLA2 / SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts

DS4830A User’s Guide 226 SR Shift Accumulator Right SRA / SRA2 / SRA4 Shift Accumulator Right Arithmeti

DS4830A User’s Guide 227 SRA2 Operation: 15 Active Accumulator (Acc) 0 Carry Flag Acc.[13:0]

DS4830A User’s Guide 228 SUB / SUBB src Subtract / Subtract with Borrow Description: Subtracts the specified src from the

DS4830A User’s Guide 229 XCH Exchange Accumulator Bytes Description: Exchanges the upper and lower bytes of the active accumulato

DS4830A User’s Guide 23 BROWNOUT STATECPU DISABLEDANALOG ACTIVESYSTEM CLOCKSTARTUP DELAY CPU MODEDIGITAL CORE ONANALOG ONCODE EXECUTIONVDD >

DS4830A User’s Guide 230 XOR src Logical XOR Description: Performs a logical-XOR between the acti

DS4830A User’s Guide 231 SECTION 25 – UTILITY ROM 25.1 – Overview The DS4830A utility ROM includes routines that provide the following functio

DS4830A User’s Guide 232 25.2 – In-Application Programming Functions 25.2.1 – UROM_flashWrite Function UROM_flashWrite Summary Programs a s

DS4830A User’s Guide 233 25.3 – Data Transfer Functions The DS4830A cannot access data from the same memory segment that is currently being use

DS4830A User’s Guide 234 25.3.3 – UROM_moveDP0dec Function UROM_moveDP0dec Summary Reads the byte/word value pointed to by DP[0], then decrem

DS4830A User’s Guide 235 25.3.6 – UROM_moveDP1dec Function UROM_moveDP1dec Summary Reads the byte/word value pointed to by DP[1], then decrem

DS4830A User’s Guide 236 25.3.9 – UROM_moveBPdec Function UROM_moveBPdec Summary Reads the byte/word value pointed to by BP[OFFS], then decrem

DS4830A User’s Guide 237 25.4 Special Functions The DS4830A provides software reset and read single word functions. 25.4. 1 – UROM_copyWord

DS4830A User’s Guide 238 25.5 – Utility ROM Examples 25.5.1 – Reading Constant Word Data from Flash UROM_moveDP0inc equ 08487h move DPC,

DS4830A User’s Guide 239 SECTION 26 – MISCELLANEOUS 26.1 – Overview Miscellaneous features of DS4830A are • CRC8 • Software interrupts •

DS4830A User’s Guide 24 2.6.4 – Internal System Resets There are two possible sources of internal system resets. An internal reset will hold

DS4830A User’s Guide 240 26.3.1 – User Interrupt Register (USER_INT) Bit 7 6 5 4 3 2 1 0 Name SW_F3 SW_F2 SW_F1 SW_F0 SW_INT4 SW_INT 3 SW_INT

DS4830A User’s Guide 25 SECTION 3 – SYSTEM REGISTER DESCRIPTIONS Most functions of the DS4830A are controlled by sets of registers. These regis

DS4830A User’s Guide 26 Table 3-2. System Register Bit Functions REGISTER REGISTER BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AP

DS4830A User’s Guide 27 3.1 – Accumulator Pointer Register (AP, 08h[00h]) Initialization: This register is cleared to 00h on all forms of res

DS4830A User’s Guide 28 3.4 – Interrupt and Control Register (IC, 08h[05h]) Initialization: This register is cleared to 00h on all forms of re

DS4830A User’s Guide 29 3.7 – Interrupt Identification Register (IIR, 08h[0Bh]) Initialization: This register is cleared to 00h on all forms o

DS4830A User’s Guide 3 3.18 – General Register (GR, 0Eh[05h]) ...

DS4830A User’s Guide 30 3.11 – Instruction Pointer Register (IP, 0Ch[00h]) Initialization: This register is cleared to 8000h on all forms of r

DS4830A User’s Guide 31 3.17 – Data Pointer Control Register (DPC, 0Eh[04h]) Initialization: This register is cleared to 001Ch on all forms of

DS4830A User’s Guide 32 3.21 – General Register Byte-Swapped (GRS, 0Eh[08h]) Initialization: This register is cleared to 0000h on all forms of

DS4830A User’s Guide 33 SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS Reg M0 M1 M2 M3 M4 M5 0 PO2 I2CBUF_M I2CBUF_S MCNT ADCN QTDATA 1 PO1 I2CST

DS4830A User’s Guide 34 4.1 – Module 0 Peripheral Registers MODULE 0 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PO2 00h

DS4830A User’s Guide 35 4.2 – Module 1 Peripheral Registers MODULE 1 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CBUF_M 00h D[15:0

DS4830A User’s Guide 36 4.3 – Module 2 Peripheral Registers MODULE 2 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2CBUF_S 00h D[15:0]

DS4830A User’s Guide 37 4.4 – Module 3 Peripheral Registers MODULE 3 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MCNT 00h

DS4830A User’s Guide 38 4.5 – Module 4 Peripheral Registers MODULE 4 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCN

DS4830A User’s Guide 39 4.6 – Module 5 Peripheral Registers MODULE 5 Register index 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 QTDATA 00h QTDATA[1

DS4830A User’s Guide 4 7.1.10 – ADC Data Reading ...

DS4830A User’s Guide 40 SECTION 5 – INTERRUPTS The DS4830A provides a single, programmable interrupt vector (IV) that can be used to handle int

DS4830A User’s Guide 41 Note: Some of the DS4830A module and peripheral interrupts sources are shown in the Figure 5-1 interrupt hierarchy d

DS4830A User’s Guide 42 INTERRUPT INTERRUPT FLAG LOCAL ENABLE BIT MODULE INTERRUPT IDENTIFICATION BIT INTERRUPT IDENTIFICATION BIT MODULE ENA

DS4830A User’s Guide 43 enable bits and combined to create a single interrupt identification bit for that specific function. For example, the I

DS4830A User’s Guide 44 1. The next instruction fetch from program memory is cancelled. 2. The return address is pushed on to the stack. 3.

DS4830A User’s Guide 45 SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC) The DS4830A contains eight 12-bit digital-to-analog converters (DACs). E

DS4830A User’s Guide 46 DS4830A IC data sheet). The DAC output voltage is maintained during any type of reset except POR. All DACs, REFINA and

DS4830A User’s Guide 47 6.2.2 – DAC Data Registers (DACD0-DACD7) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - - DACDx[11:0] Reset 0 0

DS4830A User’s Guide 48 SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC) The DS4830A provides a 13-bit analog-to-digital converter (ADC) with 26-i

DS4830A User’s Guide 49 Table 7-1: ADC Configuration and Data Buffers DATA BUFFER CONFIGURATION/DATA BUFFER SELECTION 0-15 External Channels (0

DS4830A User’s Guide 5 10.1.7 – Transmitting a Slave Address ...

DS4830A User’s Guide 50 is stopped. Writing a ‘0’ to the ADCONV bit stops the ADC operation at the completion of the current ADC conversion

DS4830A User’s Guide 51 7.1.4 – Sample and Hold Conversion The DS4830A has two Sample and Hold (S/H) inputs at pins GP2-GP3 and GP12-GP13. Thes

DS4830A User’s Guide 52 7.1.7 – ADC Conversion Time The ADC clock is derived from the system clock with a divide ratio defined by the ADC Clock

DS4830A User’s Guide 53 10 111 2 3 4 5 6 7 8 9 18161514131228 2919 20 21 22 23 24 25 26 2717 30...1 19 20ADACQSAMPLE 1HOLD AND CONVERT SAMPLE 1

DS4830A User’s Guide 54 Figure 7-5 shows the ADC frame sequence for the following programmed sequence of ADC channels. 1. CH0: Average of 4 Sa

DS4830A User’s Guide 55 For example, if ADSTART = 0, ADEND = 6 and NUM_SMP = 3 with ADDAINV = 1, then ADDAI is set to ‘1’ after every (NUM_SMP

DS4830A User’s Guide 56 7.2 – ADC Register Descriptions The ADC is controlled by the ADC SFR registers. The PINSEL register is used to configur

DS4830A User’s Guide 57 7.2.2 – ADC Status Register (ADST) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - - ENALE_2X - - - ADCAVG ADCONV

DS4830A User’s Guide 58 7.2.4 – ADC Status Register (ADST1) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - - - - - - - SH1DAI SH0DAI -

DS4830A User’s Guide 59 7.2.6.1 – ADC Configuration Register (ADDATA when ADCFG = 1 and ADCAVG = 0) When ADCFG = 1 and ADCAVG = 0, writing to t

DS4830A User’s Guide 6 SECTION 13 – 3-WIRE ...

DS4830A User’s Guide 60 7.2.6.2 – ADC Average Register (ADDATA when ADCAVG = 1 and ADCFG = 0) When ADCAVG = 1 and ADCFG = 0, writing to the ADD

DS4830A User’s Guide 61 7.2.8 – Temperature Control Register (TEMPCN) The Temperature Control register TEMPCN configures and enables internal

DS4830A User’s Guide 62 7.2.10 – ADC Voltage Offset Register (ADVOFF) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name S S S 212 211 210 29 28 2

DS4830A User’s Guide 63 7.3 – ADC Code Examples 7.3.1 – One Sequence of 4 Voltage Conversions for Ch0 (Diff), Ch1 (Diff), Ch14 (Single), and Ch

DS4830A User’s Guide 64 ADST_bit.ADCFG = 0; //set ADDATA to data buffer ADADDR_bit.ADSTART = 0; //start sequence with ADCFG [0] ADADDR_bit.A

DS4830A User’s Guide 65 SECTION 8 – SAMPLE AND HOLD The DS4830A has two independent, but identical, Sample and Hold differential channels. Sam

DS4830A User’s Guide 66 For proper first sample capturing on power up, the sample and hold should be initialized as explained below. 1. Enable

DS4830A User’s Guide 67 channels and hence their ADC conversion will be delayed. When the FAST_MODE bit is set to ‘0’, the user can issue SHEN

DS4830A User’s Guide 68 SHEN0/1 orINT_REIG0/1Sample PulseSample Pulse Width with external clockCLKIN….Falling edge (Sample stop) depends upon

DS4830A User’s Guide 69 8.1.5 – Sample and Hold Data Reading Each sample and hold has defined data buffer locations where the ADC controller wr

DS4830A User’s Guide 7 18.4.1 – Accessing the Multiplier ...

DS4830A User’s Guide 70 8.2 – Sample and Hold Register Descriptions The sample and hold has two SFRs. These are Sample and Hold Control Registe

DS4830A User’s Guide 71 this bit is ‘0’, Sample and Hold 0 acts in the normal mode in which Sample and Hold 0 gets a conversion slot in the ADC

DS4830A User’s Guide 72 8.2.2 – Sample and Hold Internal Trigger Enable Register (SENR) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name INT_

DS4830A User’s Guide 73 SECTION 9 – QUICK TRIP (FAST COMPARATOR) The DS4830A has 10-bit quick trips with a 16-input analog MUX (Figure 9-1). Th

DS4830A User’s Guide 74 By default, the external channels GP0-15 are general-purpose input. The DS4830A has the Pin Select Register (PINSEL).

DS4830A User’s Guide 75 times in the QT list). The quick trip list can be filled sequentially with data 05h (channel 5 + single-ended), 06h (ch

DS4830A User’s Guide 76 Table 9-4: Quick Trip High Threshold Configuration QTCN = 0x0010; //High Threshold Configuration Register, In

DS4830A User’s Guide 77 9.2 – Quick Trip Register Descriptions The quick trip has 7 SFRs. These are the Quick Trip Control Register (QTCN), Qui

DS4830A User’s Guide 78 QTDATA Register map when RW_LST = 0 (in the QTCN Register) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - LOW or HIGH

DS4830A User’s Guide 79 9.2.3 Low Trip Interrupt Lower Register (LTIL) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name IE[7:0] IF[7:0] Reset

DS4830A User’s Guide 8 22.3.4 – Command 03h – Password Match ...

DS4830A User’s Guide 80 9.2.5 Low Trip Interrupt High Register (LTIH) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name IE[15:8] IF[15:8] Reset

DS4830A User’s Guide 81 SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE The DS4830A provides an I2C-compatible master controller that allows the

DS4830A User’s Guide 82 Figure 10-1: I2C Clock Generation The master I2C controller’s ability to monitor the state of SCL allows the master

DS4830A User’s Guide 83 For all of these cases, when the I2C timeout period is reached, the I2CTOI flag will be set. The setting of I2CTOI ca

DS4830A User’s Guide 84 Timeout ?I2CTOI=1NYNYGenerate STARTI2CSTART=1I2CSTART=0I2CBUSY=0I2CBUSY=1RepeatedStart?I2CBUS = 1NYSTARTDetected?I2CS

DS4830A User’s Guide 85 10.1.6 – Generating a STOP To end an I2C transfer, a STOP must be transmitted. A STOP is generated by setting the I2CS

DS4830A User’s Guide 86 to be set. Once set, writes to I2CBUF_M will be ignored. The first bit of data (most significant bit) will be shifted

DS4830A User’s Guide 87 10.1.9 – Receiving Data The DS4830A I2C Master Controller enters data reception mode after transmitting a slave addres

DS4830A User’s Guide 88 10.1.10 – I2C Master Clock Stretching The Master I2C Controller is capable of clock stretching at the end of each trans

DS4830A User’s Guide 89 10.1.12 – Alternate Location The DS4830A has 3-Wire, SPI and I2C Master on the same pins and some application may nee

DS4830A User’s Guide 9 23.7.2 – Unconditional Jumps ...

DS4830A User’s Guide 90 10.2 – I2C Master Controller Register Description Following are the registers that are used to control the I2C Master I

DS4830A User’s Guide 91 10.2.2 – I2C Master Status Register (I2CST_M) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I2CBUS I2CBUSY - I2CAMI2

DS4830A User’s Guide 92 10.2.3 – I2C Master Interrupt Enable Register (I2CIE_M) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name - - - - I2CSPIE

DS4830A User’s Guide 93 10.2.5 – I2C Master Clock Control Register (I2CCK_M) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I2CCKH[7:0] I2CCKL

DS4830A User’s Guide 94 SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE The DS4830A provides an I2C-compatible slave controller that allows communi

DS4830A User’s Guide 95 11.1 – Detailed Description The I2C slave controller has two different modes that can be used to transmit and receive d

DS4830A User’s Guide 96 Matched Slave Address CUR_SLA.SLA[3:0] I2CSLA_S 1 I2CSLA2_S 2 I2CSLA3_S 4 I2CSLA4_S 8 • Clears the I2CBUSY flag. Upon

DS4830A User’s Guide 97 11.1.6 – Advanced Mode Operation RX FIFO and TX Pages The DS4830A I2C slave controller has a few features that make 400

DS4830A User’s Guide 98 Detect I2C StartI2CSRI = 1I2CBUS = 1I2CBUSY = 1ReceiveAddr[6:0] + /R\WMatched Enabled Slave AddressesTransmit I2CACKSet

DS4830A User’s Guide 99 • Sets the I2CST_S.I2CTXI flag to indicate that the I2C slave controller has transmitted a byte. This can generate an