Maxim-integrated Sonoma (MAXREFDES14) ZedBoard Manual do Utilizador descarregar pdf (Página 5)

Sonoma (MAXREFDES14#) ZedBoard Quick Start Guide

3. Included Files

The top level of the hardware design is a Xilinx PlanAhead Project (.prr) for Xilinx

PlanAhead version 14.2. The Verilog-based arm_system_stub.v module provides

FPGA/board net connectivity, and instantiates the wrapper that carries the Zynq®

Processing System. This is supplied as a Xilinx software development kit (SDK) project

that includes a demonstration software application to evaluate the Sonoma subsystem

reference design. The lower level c-code driver routines are portable to the user’s own

software project.

Figure 3. Block Diagram of FPGA Hardware Design

1 2 3 4 5 6 7 8 9 10 ... 20 21

Sem comentários

Maxim-integrated Sonoma (MAXREFDES14) ZedBoard Manual do Utilizador Página 5