Maxim-integrated DS4830 Optical Microcontroller Manual do Utilizador Página 131
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DS4830 User’s Guide
131
15.3.3 – GPIO Input Register for Port 1 (PI1)
Bit #
7
6
5
4
3
2
1
0
Name
PI1_7
PI1_6
PI1_5
PI1_4
PI1_3
PI1_2
PI1_1
PI1_0
Reset
s
s
s
s
s
s
s
s
Access
r
r
r
r
r
r
r
r
PI1 is an 8-bit register which contains the data that is applied to the GPIO pins. The PI1 input register contains valid input
data even when the pin is not operating as a GPIO. The reset value for this register is dependent on the logical states
applied to the pins. Note that each pin has a weak pull-up circuit when functioning as an input and the P channel pull-up
transistor is controlled by the PO1.n bit.
15.3.4 – GPIO Port 1 External Interrupt Edge Select Register (EIES1)
Bit #
7
6
5
4
3
2
1
0
Name
IT7
IT6
IT5
IT4
IT3
IT2
IT1
IT0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
The EIES1 register sets the interrupt edge select to trigger an interrupt on either a rising or falling edge. Setting the
IESP1_n bits to 0 will trigger the corresponding interrupt on a positive edge. When these bits are set to a 1, the interrupt
will be on a negative edge.
15.3.5 – GPIO Port 1 External Interrupt Flag Register (EIF1)
Bit #
7
6
5
4
3
2
1
0
Name
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
These bits are set when a negative edge (IESP1.n = 1) or a positive edge (IESP1.n = 0) is detected on the P1.n pin.
Setting any of the bits to 1 will generate an interrupt to the CPU if the corresponding interrupt is enabled. These bits will
remain set until cleared by software or a reset. These bits must be cleared by software before exiting the interrupt service
routine or another interrupt will be generated as long as the bit remains set.
15.3.6 – GPIO Port 1 External Interrupt Enable Register (EIE1)
Bit #
7
6
5
4
3
2
1
0
Name
EX7
EX6
EX5
EX4
EX3
EX2
EX1
EX0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
Setting any of these bits to 1 will enable the corresponding external interrupt. Clearing any of the bits to 0 will disable the
corresponding interrupt function.
15.4 – GPIO Port 2 Register Descriptions
Port 2 provides eight GPIO pins that are multiplexed with the ADC, PWM, DAC and External reference (REFINA). ADC
function is enabled when PINSEL.n is set to ‘1’ (where n = 0, 1, 6 to 9). Single or Differential ADC mode is selected by
ADDATA.DIFF bit during ADC configuration (when ADCN.CFG is set to ‘1’). DAC function is enabled when DACCFG.n is
set to either “10b” or “01b” (where n = 7). PWM is enabled when corresponding PWM local enable and PWM master
enable is set to ‘1’. REFINA (Pin2.6) is configured as external reference when DACCFG.n is set to “01b” for any DACn
(where n = 0 to 3).
Port 2 also provides GPIO interrupts on all of the pins. A GPIO interrupt can be generated when the pin is being operated
as a GPIO, or a special. Three additional registers, EIF2, EIE2, and EIES2 are used to control the GPIO interrupts
15.4.1 – GPIO Direction Register Port 2 (PD2)
Bit #
7
6
5
4
3
2
1
0
Name
PD2_7
PD2_6
PD2_5
PD2_4
PD2_3
PD2_2
PD2_1
PD2_0
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
- OpticalMicrocontroller 1
- User’sGuide 1
- Contents 2
- SECTION 1 – OVERVIEW 9
- DS4830 User’s Guide 10
- SECTION 2 – ARCHITECTURE 11
- 2.2 – Register Space 12
- 2.3 – Memory Types 13
- 2.5 – Data Alignment 20
- 2.6 – Reset Conditions 20
- 2.7 – Clock Generation 22
- SECTION 5 – INTERRUPTS 36
- 5.1 – Servicing Interrupts 37
- 6.1 – Detailed Description 42
- 6.3 – DAC Code Examples 45
- 7.1 – Detailed Description 46
- 7.3 – ADC Code Examples 58
- SECTION 8 – SAMPLE AND HOLD 60
- 9.1 – Detailed Description 68
- SECTION 10 – I 76
- SECTION 11 – I 89
- C-COMPATIBLE SLAVE INTERFACE 89
- 11.1 – Detailed Description 90
- 12.2 – SPI System Errors 101
- 12.3 – SPI Interrupts 102
- SECTION 13 – 3-WIRE 110
- Using PWMCN and PWMDATA 113
- Core Clock 120
- FrequencyClockPWM 123
- FrequencyFramePWM 123
- * = 01b 127
- MULTIPLIER 140
- SECTION 19 – WATCHDOG TIMER 146
- 20.1 – TAP Controller 150
- 20.2 – TAP State Control 151
- 20.3 – Communication via TAP 152
- 21.2 – Debug Mode 160
- 22.1 – Detailed Description 169
- 22.2 – Bootloader Operation 171
- 22.3 – Bootloader Commands 173
- SECTION 23 – PROGRAMMING 179
- SECTION 24 – INSTRUCTION SET 192
- SECTION 25 – UTILITY ROM 220
- 25.4 – Utility ROM Examples 227
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