Maxim-integrated DS4830 Optical Microcontroller Manual do Utilizador Página 87
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DS4830 User’s Guide
87
10.2.3 – I
2
C Master Interrupt Enable Register (I2CIE_M)
Address: M1[02h]
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
-
-
-
-
I2CSPIE
-
I2CROIE
I2CGCIE
I2CNACKIE
-
I2CAMIE
I2CTOIE
I2CSTRIE
I2CRXIE
I2CTXIE
I2CSRIE
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
r
r
r
r
rw
r
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:12
Reserved
Reserved. The user should write 0 to these bits.
11
I2CSPIE
I
2
C Master STOP Interrupt Enable. Setting this bit to ‘1’ will enable an interrupt
when a STOP condition is detected (I2CSPI=1). Clearing this bit to ‘0’ will disable
the STOP detection interrupt.
10
Reserved
Reserved. The user should not write to this bit.
9
I2CROIE
I
2
C Master Receiver Overrun Interrupt Enable. Setting this bit to ‘1’ will enable
an interrupt when a receiver overrun condition is detected (I2ROI=1). Clearing this
bit to ‘0’ will disable the receiver overrun detection interrupt.
8
I2CGCIE
I
2
C General Call Interrupt Enable. This bit has no function when operating in
master mode.
7
I2CNACKIE
I
2
C Master NACK Interrupt Enable. Setting this bit to ‘1’ will enable an interrupt
when a NACK is detected (I2CNACKI=1). Clearing this bit to ‘0’ will disable the
NACK detection interrupt.
6
Reserved
Reserved. The user should write 0 to this bit.
5
I2CAMIE
I
2
C Address Match Interrupt Enable. This bit has no function when operating in
master mode.
4
I2CTOIE
I
2
C Master Timeout Interrupt Enable. Setting this bit to ‘1’ will enable an
interrupt when a timeout condition is detected (I2CTOI=1). Clearing this bit to ‘0’
will disable the timeout interrupt.
3
I2CSTRIE
I
2
C Master Clock Stretch Interrupt Enable. Setting this bit to ‘1’ will enable an
interrupt when the clock stretch interrupt flag is set (I2CSTRI=1). Clearing this bit
will disable the clock stretch interrupt.
2
I2CRXIE
I
2
C Master Receive Ready Interrupt Enable. Setting this bit to ‘1’ will enable an
interrupt when receive ready interrupt flag is set (I2CRXI=1). Clearing this bit to ‘0’
will disable the receive ready interrupt.
1
I2CTXIE
I
2
C Master Transmit Complete Interrupt Enable. Setting this bit to ‘1’ will enable
an interrupt when transmit complete interrupt flag is set (I2CTXI=1). Clearing this
bit to ‘0’ disables transmit complete interrupt.
0
I2CSRIE
I
2
C Master START Interrupt Enable. Setting this bit to ‘1’ will enable an interrupt
when a START condition is detected (I2CSRI=1). Clearing this bit to ‘0’ will
disable the START detection interrupt.
10.2.4 – I
2
C Master Data Buffer Register (I2CBUF_M)
Address: M1[00h]
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
-
-
-
-
-
-
-
-
D7
D6
D5
D4
D3
D2
D1
D0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
r
r
r
r
r
r
r
r
rw*
rw*
rw*
rw*
rw*
rw*
rw*
rw*
* Unrestricted read access. This register can be written to only when I2CBUSY = 0.
BIT
NAME
DESCRIPTION
15:8
Reserved
Reserved. The user should write 0 to these bits.
7:0
D[7:0]
Data for I
2
C transfer is read from or written to this location. The I
2
C transmit and receive buffers are
separate but both are addressed at this location.
- OpticalMicrocontroller 1
- User’sGuide 1
- Contents 2
- SECTION 1 – OVERVIEW 9
- DS4830 User’s Guide 10
- SECTION 2 – ARCHITECTURE 11
- 2.2 – Register Space 12
- 2.3 – Memory Types 13
- 2.5 – Data Alignment 20
- 2.6 – Reset Conditions 20
- 2.7 – Clock Generation 22
- SECTION 5 – INTERRUPTS 36
- 5.1 – Servicing Interrupts 37
- 6.1 – Detailed Description 42
- 6.3 – DAC Code Examples 45
- 7.1 – Detailed Description 46
- 7.3 – ADC Code Examples 58
- SECTION 8 – SAMPLE AND HOLD 60
- 9.1 – Detailed Description 68
- SECTION 10 – I 76
- SECTION 11 – I 89
- C-COMPATIBLE SLAVE INTERFACE 89
- 11.1 – Detailed Description 90
- 12.2 – SPI System Errors 101
- 12.3 – SPI Interrupts 102
- SECTION 13 – 3-WIRE 110
- Using PWMCN and PWMDATA 113
- Core Clock 120
- FrequencyClockPWM 123
- FrequencyFramePWM 123
- * = 01b 127
- MULTIPLIER 140
- SECTION 19 – WATCHDOG TIMER 146
- 20.1 – TAP Controller 150
- 20.2 – TAP State Control 151
- 20.3 – Communication via TAP 152
- 21.2 – Debug Mode 160
- 22.1 – Detailed Description 169
- 22.2 – Bootloader Operation 171
- 22.3 – Bootloader Commands 173
- SECTION 23 – PROGRAMMING 179
- SECTION 24 – INSTRUCTION SET 192
- SECTION 25 – UTILITY ROM 220
- 25.4 – Utility ROM Examples 227
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