Maxim-integrated High-Speed Microcontroller Users Guide: DS80C390 S Manual do Utilizador

AVAILABLE1 of 158 REV: 081606 This document is provided as a supplement to the High-Speed Microcontroller User’s Guide, covering new or modified feat

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 10 of 158 REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESSSAD

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 100 of 158 ADDENDUM TO SECTION 7: POWER MANAGEMENT The DS80C390 supports the general po

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 101 of 158 ADDENDUM TO SECTION 8: RESET CONDITIONS This section supersedes the correspo

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 102 of 158 EXTERNAL RESET If the RST input is taken to a logic 1, the CPU will be force

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 103 of 158 contents are not altered. Interrupts and Timers are disabled. The state of t

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 104 of 158 ADDENDUM TO SECTION 10: PARALLEL I/O Changes to this section primarily invo

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 105 of 158 OUTPUT FUNCTIONS Although 8051 I/O ports appear to be true I/O, their output

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 106 of 158 ADDENDUM TO SECTION 11: PROGRAMMABLE TIMERS The timers of the DS80C390 are v

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 107 of 158 01T0M = CKCON.3(T1M = CKCON.4)T0 = P3.4(T1 = P3.5)C/T = TMOD.2(C/T = TMOD.6

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 108 of 158 TIMER/COUNTER 2 CLOCK-OUT MODE (/RL2 = 0) TIMER/COUNTER 2 BAUD RATE GENE

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 109 of 158 TIMER/COUNTER 2 AUTO RELOAD MODE (/RL2 = 0) (A) DCEN = 0 TIMER/COUNTER 2 A

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 11 of 158 REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESSMXA

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 110 of 158 DIVIDE-BY-13 OPTION The other change to the timers associated with the DS80C

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 111 of 158 IrDA CLOCK OUTPUT The Infrared Data Association (IrDA) communication protoco

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 112 of 158 ADDENDUM TO SECTION 12: SERIAL I/O The serial ports of the DS80C390’s Ax and

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 113 of 158 ADDENDUM TO SECTION 13: TIMED ACCESS PROTECTION A number of timed-access pro

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 114 of 158 ADDENDUM TO SECTION 16: INSTRUCTION SET DETAILS The DS80C390 supports one of

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 115 of 158 The DS80C390 supports interrupts from any location in the 22-bit address fie

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 116 of 158 The modification of the instructions in the 22-bit page address mode is summ

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 117 of 158 software tools (assembler or compiler) specifically designed to accept the m

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 118 of 158 INSTRUCTION CODE MNEMONIC D7 D6 D5 D4 D3 D2D1D0 HEX BYTE CYCLE EXP

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 119 of 158 SECTION 19: CONTROLLER AREA NETWORK (CAN) MODULE (DS80C390 Supplement Only)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 12 of 158 REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESSP5C

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 120 of 158 MOVX MESSAGE CENTERS FOR CAN 0 CAN 0 CONTROL/STATUS/MASK REGISTERS Register

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 121 of 158 CAN 0 MESSAGE CENTERS 2-14 MESSAGE CENTER 2 REGISTERS (similar to Message

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 122 of 158 MOVX MESSAGE CENTERS FOR CAN 1 CAN 1 CONTROL/STATUS/MASK REGISTERS Register

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 123 of 158 CAN 1 MESSAGE CENTERS 2-14 MESSAGE CENTER 2 REGISTERS (similar to Message

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 124 of 158 CAN MOVX REGISTER DESCRIPTION Most of the SRAM control registers, including

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 125 of 158 CnMID0 masks programmed to 1 will force the state of the corresponding Data

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 126 of 158 can only be modified during a software initialization (SWINT=1). BPR5 BPR4

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 127 of 158 TSEG13 TSEG12 TSEG11 TSEG10 Time Segment One Length (Number in parenthe

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 128 of 158 CAN Extended Global Mask Register 0 (CnEGM0) MOVX Address1 7 6 5 4 3 2

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 129 of 158 CAN Message Center 15 Mask Register 0 (CnM15M0) MOVX Address1 7 6 5 4 3

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 13 of 158 REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESSC1C

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 130 of 158 CAN MESSAGE CENTER MOVX REGISTER DESCRIPTIONS CAN Message Center y Arbitrat

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 131 of 158 WTOE DTUP EXTRQ Result when new message detected 0 0 0 There is current

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 132 of 158 CAN Message Center y Format Register (CnMyF) MOVX Address1 7 6 5 4 3 2

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 133 of 158 CAN Message Center y Data Byte 0 (CnMyD0) MOVX Address1 7 6 5 4 3 2 1

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 134 of 158 FRAME TYPES The CAN 2.0B protocol specifies two different message formats, t

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 135 of 158 The Substitution Remote Request bit is a recessive bit and is substituted fo

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 136 of 158 Figure 19-4. CRC FIELD CRC FieldCRC SequenceCRC DelimiterData Field orContro

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 137 of 158 Remote Frame (Standard and Extended Format) The Remote Frame is transmitted

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 138 of 158 until six equal bits of the same polarity have been detected. At this point

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 139 of 158 INITIALIZING THE CAN CONTROLLERS Software initialization of each CAN control

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 14 of 158 PORT 4 (P4) 7 6 5 4 3 2 1 0 SFR 80h A19/P4.7 A18/P4.6 A17/P4.5 A18/P4.4

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 140 of 158 SFR Register. Software must clear the respective INTRQ bit in the associated

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 141 of 158 ARBITRATION/MASKING CONSIDERATIONS Each CAN processor evaluates CAN bus acti

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 142 of 158 message center 15). This AND’ed value is then used in place of CnEGM3-0 or C

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 143 of 158 have DTUP = 1, which will in turn set ROW = 1. When WTOE = 0, incoming messa

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 144 of 158 to the remote frame request. Higher numbered message centers (lower priority

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 145 of 158 Case 1: Automatic Reply CAN Controller receives a remote frame Request (RFR)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 146 of 158 6. CAN waits for Software to read message center and determine the fact tha

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 147 of 158 REMOTE FRAME HANDLING IN RELATION TO THE DTBYC BITS The DTBYC bits function

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 148 of 158 overwrite the message center. If this overwrite occurs at the same time that

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 149 of 158 7. Software reads message center 2 and then programs message center 2 DTUP

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 15 of 158 STACK POINTER (SP) 7 6 5 4 3 2 1 0 SFR 81h SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 150 of 158 If, after a period of time, only a small number of errors have accumulated (

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 151 of 158 CONDITION EFFECT ON ERROR COUNTERS Error detected by receiver, unless the de

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 152 of 158 A node is bus off when the transmit error count is greater than or equal to

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 153 of 158 Figure 19-11. BIT TIMING The CAN 0/1 Bus Timing Register Zero (C0BT0/C1BT0)

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 154 of 158 The timing of the various time segments is determined by the following formu

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 155 of 158 maximum bit time = tSYNC_SEG + tTSEG1 + tTSEG2 + tSJW = OSCF)]SJW()LEN_2T

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 156 of 158 SECTION 20: ARITHMETIC ACCELERATOR (DS80C390 Supplement Only) The DS80C390 i

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 157 of 158 USING THE ARITHMETIC ACCELERATOR The following procedures illustrate how to

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 158 of 158 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circu

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 16 of 158 DATA POINTER HIGH 1 (DPH1) 7 6 5 4 3 2 1 0 SFR 85h DPH1.7 DPH1.6 DPH1.5 DP

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 17 of 158 POWER CONTROL (PCON) 7 6 5 4 3 2 1 0 SFR 87h SMOD_0 SMOD0 OFDF ODFE F

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 18 of 158 TIMER/COUNTER CONTROL (TCON) 7 6 5 4 3 2 1 0 SFR 88h TF1 TR1 TF0 TR0 IE1 IT

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 19 of 158 TIMER MODE CONTROL (TMOD) 7 6 5 4 3 2 1 0 SFR 89h GATE C/T M1 M0 GATE C/ T

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 2 of 158 PORT 5 CONTROL REGISTER (P5CNT) ...

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 20 of 158 TIMER 0 LSB (TL0) 7 6 5 4 3 2 1 0 SFR 8Ah TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 21 of 158 CLOCK CONTROL (CKCON) 7 6 5 4 3 2 1 0 SFR 8Eh WD1 WD0 T2M T1M T0M MD2 MD1

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 22 of 158 MD2, MD1, MD0 Bits 2-0 Stretch MOVX Select 2-0. These bits select the time b

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 23 of 158 RXD1 Bit 2 Serial Port 1 Receive. This pin receives the serial port 1 data i

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 24 of 158 RGSL Bit 1 Ring Oscillator Select. This bit selects the clock source followi

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 25 of 158 110 I/O A18 A17 A16 512 kbytes 111 A19 A18 A17 A16 1 Mbytes P4CNT.2-P4CNT

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 26 of 158 CAN 0 RECEIVE MESSAGE STORED REGISTER 0 (C0RMS0) 7 6 5 4 3 2 1 0 SFR 96h C

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 27 of 158 CAN 0 RECEIVE MESSAGE STORED REGISTER 1 (C0RMS1) 7 6 5 4 3 2 1 0 SFR 97h

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 28 of 158 SERIAL PORT 0 CONTROL (SCON0) 7 6 5 4 3 2 1 0 SFR 98h SM0/FE_0 SM1_0 SM

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 29 of 158 TB8_0 Bit 3 9th Transmission Bit State. This bit defines the state of the 9

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 3 of 158 EXTENDED INTERRUPT ENABLE (EIE) ...

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 30 of 158 EXTENDED STACK POINTER REGISTER (ESP) 7 6 5 4 3 2 1 0 SFR 9Bh 1 1 1 1 1 1 E

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 31 of 158 ADDRESS CONTROL REGISTER (ACON) 7 6 5 4 3 2 1 0 SFR 9Dh 1 1 1 1 1 SA AM1 AM

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 32 of 158 CAN 0 TRANSMIT MESSAGE ACKNOWLEDGEMENT REGISTER 0 (C0TMA0) 7 6 5 4 3 2 1 0

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 33 of 158 CAN 0 TRANSMIT MESSAGE ACKNOWLEDGEMENT REGISTER 1 (C0TMA1) 7 6 5 4 3 2 1 0

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 34 of 158 PORT 2 (P2) 7 6 5 4 3 2 1 0 SFR A0h A15/P2.7 A14/P2.6 A13/P2.5 A12/P2.4

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 35 of 158 External Connection bit (SP1EC, P5CNT.5) configures this pin as the Serial P

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 36 of 158 established by the P4CNT register. Note that the chip-enable range when usin

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 37 of 158 power-down mode. Power-down mode is exited by clearing the PDE bit or by any

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 38 of 158 ERCS Bit 1 CAN 0 Error Count Select. This bit selects the number of transmit

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 39 of 158 CAN 0 STATUS REGISTER (C0S) 7 6 5 4 3 2 1 0 SFR A4h BUSOFF CECE WKS RX

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 4 of 158 SECTION 19: CONTROLLER AREA NETWORK (CAN) MODULE ...

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 40 of 158 RXS Bit 4 CAN 0 Receive Status. This bit indicates whether or not messages h

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 41 of 158 TXS bit in the Status Register, a second status change interrupt flag will b

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 42 of 158 arbitration field (identifier and remote retransmission request). Bit 0 Err

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 43 of 158 first interrupt source detected by the CAN module following the non-active i

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 44 of 158 CAN 0 RECEIVE ERROR REGISTER (C0RE) 7 6 5 4 3 2 1 0 SFR A7h R*-0

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 45 of 158 ET0 Bit 1 Enable Timer 0 Interrupt. This bit controls the masking of the Ti

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 46 of 158 CAN 0 MESSAGE CENTER 1 CONTROL REGISTER (C0M1C) 7 6 5 4 3 2 1 0 SFR ABh M

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 47 of 158 transmission by a message center programmed for transmission (T/R = 1), the

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 48 of 158 center when the CAN is processing the incoming data. ROW is cleared by the

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 49 of 158 after the message center read. If DTUP has been set, then a new message was

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 5 of 158 ADDENDUM TO SECTION 2: ORDERING INFORMATION The high-speed microcontroller fa

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 50 of 158 CAN 0 MESSAGE CENTER 4 CONTROL REGISTER (C0M4C) 7 6 5 4 3 2 1 0 SFR AEh M

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 51 of 158 INT0 Bit 2 External Interrupt 0. A falling edge/low level on this pin will

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 52 of 158 CAN 0 MESSAGE CENTER 9 CONTROL REGISTER (C0M9C) 7 6 5 4 3 2 1 0 SFR B6h M

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 53 of 158 PT0 Bit 1 Timer 0 Interrupt. This bit controls the priority of Timer 0 inte

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 54 of 158 CAN 0 MESSAGE CENTER 11 CONTROL REGISTER (C0M11C) 7 6 5 4 3 2 1 0 SFR BBh

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 55 of 158 CAN 0 MESSAGE CENTER 15 CONTROL REGISTER (C0M15C) 7 6 5 4 3 2 1 0 SFR BFh

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 56 of 158 Mode 1: When set, reception is ignored (RI_1 is not set) if invalid stop bit

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 57 of 158 POWER MANAGEMENT REGISTER (PMR) 7 6 5 4 3 2 1 0 SFR C4h CD1 CD0 SWB CT

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 58 of 158 2. Set the CTM bit. At this point the CKRY bit (EXIF.3) will be cleared, in

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 59 of 158 SPTA0 Bit 1 Serial Port 0 Transmit Activity Monitor. When set, this bit indi

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 6 of 158 ADDENDUM TO SECTION 4: PROGRAMMING MODEL The DS80C390 microprocessor is based

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 60 of 158 PDCE2 Bit 2 Program/Data Chip Enable 2. This bit selects whether the CE2 si

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 61 of 158 TIMER 2 CONTROL (T2CON) 7 6 5 4 3 2 1 0 SFR C8h TF2 EXF2 RCLK TCLK EXEN2 T

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 62 of 158 TR2 Bit 2 Timer 2 Run Control. This bit enables/disables the operation of ti

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 63 of 158 DCEN Bit 0 Down Count Enable. This bit, in conjunction with the T2EX pin, co

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 64 of 158 TIMER 2 MSB (TH2) 7 6 5 4 3 2 1 0 SFR CDh TH2.7 TH2.6 TH2.5 TH2.4 TH2.3

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 65 of 158 CLKOE Bit 0 External Clock Output Enable. This bit enables the optional cloc

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 66 of 158 MULTIPLIER CONTROL REGISTER ZERO (MCNT0) 7 6 5 4 3 2 1 0 SFR D1h LSHIFT C

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 67 of 158 MAS4-0 Bits 4-0 Multiplier Register Shift Bits. These bits determine the num

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 68 of 158 CLM Bit 4 Clear Accelerator Registers. Writing a one to this bit will clear

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 69 of 158 MULTIPLIER C REGISTER (C) 7 6 5 4 3 2 1 0 SFR D5h RW-0 RW-0 RW-0

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 7 of 158 register. Since there are four banks, the currently selected bank will be use

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 70 of 158 C1RMS0.2 Bit 2 Message Center 3, Message Received and Stored C1RMS0.1 Bit

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 71 of 158 WATCHDOG CONTROL (WDCON) 7 6 5 4 3 2 1 0 SFR D8h SMOD POR EPF1 PFI WDI

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 72 of 158 WTRF Bit 2 Watchdog Timer Reset Flag. When set, this bit indicates that a wa

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 73 of 158 C1TMA0.3 Bit 3 Message Center 4, Message Transmitted C1TMA0.2 Bit 2 Messag

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 74 of 158 ACCUMULATOR (A or ACC) 7 6 5 4 3 2 1 0 SFR E0h ACC.7 ACC.6 ACC.5 ACC.4 ACC.

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 75 of 158 CRST Bit 3 CAN 1 Reset. Setting this bit by a Timed Access write will reset

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 76 of 158 MOVX SRAM. These bytes contain the CAN 1 Control/Status/Mask Registers. Read

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 77 of 158 CAN 1 STATUS REGISTER (C1S) 7 6 5 4 3 2 1 0 SFR E4h BUSOFF CECE WKS RX

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 78 of 158 or a system Reset. 1 = The meaning of RXS=1 is dependent on the autobaud bit

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 79 of 158 CAN Status Register has been read to clear the previous status change interr

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 8 of 158 Figure 4-1. DS80C390 MEMORY MAP (DEFAULT SETTINGS) DataMemoryProgramMemoryIn

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 80 of 158 CAN 1 INTERRUPT REGISTER (C1IR) 7 6 5 4 3 2 1 0 SFR E5h R-0 R-0

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 81 of 158 CAN 1 TRANSMIT ERROR REGISTER (C1TE) 7 6 5 4 3 2 1 0 SFR E6h — — — — — —

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 82 of 158 EXTENDED INTERRUPT ENABLE (EIE) 7 6 5 4 3 2 1 0 SFR E8h CANBIE C0IE C1IE EW

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 83 of 158 CAN 1 MESSAGE CENTER 1 CONTROL REGISTER (C1M1C) 7 6 5 4 3 2 1 0 SFR EBh M

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 84 of 158 EXTRQ bit in a similar manner, but will not automatically transmit a data fr

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 85 of 158 center, EXTRQ will be set to a 1. Following the Remote Frame Request and aft

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 86 of 158 CAN 1 MESSAGE CENTER 2 CONTROL REGISTER (C1M2C) 7 6 5 4 3 2 1 0 SFR ECh M

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 87 of 158 B REGISTER (B) 7 6 5 4 3 2 1 0 SFR F0h B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 RW

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 88 of 158 CAN 1 MESSAGE CENTER 9 CONTROL REGISTER (C1M9C) 7 6 5 4 3 2 1 0 SFR F6h M

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 89 of 158 1 = External interrupt 5 is a high priority interrupt. PX4 Bit 2 External In

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 9 of 158 SPECIAL FUNCTION REGISTERS Most of the unique features of the high-speed micr

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 90 of 158 CAN 1 MESSAGE CENTER 14 CONTROL REGISTER (C1M14C) 7 6 5 4 3 2 1 0 SFR FEh

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 91 of 158 ADDENDUM TO SECTION 5: CPU TIMING SYSTEM CLOCK SELECTION The internal clocki

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 92 of 158 Table 5-1. SYSTEM CLOCK CONFIGURATION CD1 CD0 2X4X/ NAME CLOCKS/MC MAX EXTE

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 93 of 158 ADDENDUM TO SECTION 6: MEMORY ACCESS EXTERNAL MEMORY INTERFACING The DS80C39

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 94 of 158 Table 6-2. EXTENDED ADDRESS AND CHIP ENABLE GENERATION Port 4 Pin Function

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 95 of 158 IMPLEMENTING A BOOTLOADER USING INTERNAL SRAM The internal 4 KB SRAM of the D

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 96 of 158 Figure 6-1. EXAMPLE DS80C390 PROGRAM/DATA MEMORY INTERFACE

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 97 of 158 Figure 6-2. EXTERNAL PROGRAM/DATA MEMORY MAP (INTERNAL SRAM STILL AT DEFAULT

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 98 of 158 Figure 6-3. COMBINED INTERNAL, EXTERNAL PROGRAM/DATA MEMORY MAP

High-Speed Microcontroller User’s Guide: DS80C390 Supplement 99 of 158 Having selected the memory configuration, the following SFR settings affect t