Maxim-integrated MAXQ610 Manual do Utilizador

Functional DiagramsPin Configurations appear at end of data sheet.Functional Diagrams continued at end of data sheet.UCSP is a trademark of Maxim Inte

2-6MAXQ610 User’s Guide2.3 Memory OrganizationBeyond the internal register space, memory on the MAXQ610 microcontroller is organized accor

6-7MAXQ610 User’s GuideBits 5:0: Input/Output Direction for Port 4. The bits in this register control the input/output direction for port pins P4.0 to

6-8MAXQ610 User’s GuideEach bit in this register is set when a negative edge or a positive edge (depending on the ITn bit setting) is detected on the

6-9MAXQ610 User’s GuideEach bit in this register controls the enable for one external interrupt. If a bit is set to 1, the corresponding interrupt is

6-10MAXQ610 User’s GuideEach bit in this register controls the edge select mode for an external interrupt, as follows:0 = The internal interrupt trigg

7-1MAXQ610 User’s Guide7.1 Timer B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-2MAXQ610 User’s GuideSECTION 7: TIMER/COUNTER TYPE BThe timer/counter module allows the MAXQ610 to control a 16-bit programmable timer/counter. The

7-3MAXQ610 User’s Guide7.1.2 Timer B Mode: Capture ModeThe 16-bit capture mode is invoked by setting the CP/RLB (TBCN.0) bit to 1. Timer B, when initi

7-4MAXQ610 User’s Guide7.1.3 Timer B Mode: Up/Down Autoreload ModeThe up/down-count autoreload option is enabled by the DCEN (TBCN.4) bit. When DCEN i

7-5MAXQ610 User’s Guide7.1.5 Timer B Mode: PWM Output FunctionThe PWM output function is enabled whenever the TBCS:TBCR bit pair is nonzero. Table 7-2

7-6MAXQ610 User’s Guide7.1.5.1 Timer B Mode: Up-Counting PWM Output ModeThe 16-bit timer/counter with autoreload mode is used for the up-counting PWM

2-7MAXQ610 User’s GuideFollowing each reset, the processor automatically starts execution at address 8000h in the utility ROM, allowing utility ROM co

7-7MAXQ610 User’s GuideThe set and reset functions for the autoreload up-counting mode essentially provide the same functionality. They pro-vide a 16-

7-8MAXQ610 User’s GuideExample TBB output waveforms for the autoreload up/down-counting modes are shown below.Up/down-count PWM duty cycle can be calc

7-9MAXQ610 User’s GuideBits 12 and 11: TBB Pin Output Reset Mode, Set Mode (TBCS:TBCR). These mode bits define whether the PWM Mode output function is

7-10MAXQ610 User’s Guide7.2.2 Timer B Value Register (TBV)7.2.3 Timer B Capture/Reload Value Register (TBR)7.2.4 Timer B Compare Register (TBC)15 0Tim

8-1MAXQ610 User’s Guide8.1 Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-2MAXQ610 User’s GuideSECTION 8: IR TIMERThe MAXQ610 microcontroller provides a dedicated IR timer/counter module to simplify support for low-speed i

8-3MAXQ610 User’s GuideFigure 8-1. IR Transmit Frequency Shifting Example (IRCFME = 0)Figure 8-2. IR Transmit Carrier Generation and Carrier Modulator

8-4MAXQ610 User’s GuideThe IR timer acts as a down counter in transmit mode. An IR transmission starts when the IREN bit is set to 1 when IRMODE = 1;

8-5MAXQ610 User’s Guide8.4 IR ReceiveWhen configured in receive mode (IRMODE = 0), the IR hardware supports the IRRX capture function. The IRRXSEL[1:0

8-6MAXQ610 User’s GuideOn the first qualified event, it does the following:1) Captures the IRRX pin state and transfers its value to IRDATA. If a fa

2-8MAXQ610 User’s Guide2.3.4 Stack MemoryThe MAXQ610 implements a soft stack that uses the on-chip data memory (SRAM) for storage of p

8-7MAXQ610 User’s GuideFigure 8-6. Receive Burst-Count ExampleIRRX12 356 84 7CARRIER FREQUENCYCALCULATIONIRMT = PULSE COUNTING IRMT = PULSE COUNTINGIR

8-8MAXQ610 User’s GuideFigure 8-7. Philips Remote Encoding Example11 001 1 11 0 0 0 0011 0000 0 0IRDATAIRDATAIRRXIRRXSEL = 10bIRMTIRMT0 IRMT1 IRMT3 IR

8-9MAXQ610 User’s GuideFigure 8-8. Sony Remote Encoding Example1 101 10000011111 000000IRRXSEL = 10bIRMT_T IRMT_T IRMT_T IRMT_T IRMT_T IRMT_T IRMT_T I

8-10MAXQ610 User’s Guide8.7 IR Timer Peripheral Registers8.7.1 IR Control Register (IRCN)Bit 13: IRV Count Enable (IRVCEN). Setting this bit to 1, whi

8-11MAXQ610 User’s GuideBits 5 and 4: IR Receive Edge Select Bits (IRRXSEL[1:0]) These bits define which edge of the input signal triggers a receive c

8-12MAXQ610 User’s GuideBit 1: IR Interrupt Flag (IRIF). This flag is set to 1 during transmit when the IR timer reloads its value and in receive mode

9-1MAXQ610 User’s Guide9.1 USART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-2MAXQ610 User’s GuideSECTION 9: SERIAL I/O MODULEThe serial I/O module provides the MAXQ610 access to a universal synchronous/asynchronous receiver-

9-3MAXQ610 User’s GuideFigure 9-1. USART Mode 0DIVIDEBY 12D7D6D5D4D3D2D1D0LOADCLOCKOUTPUT SHIFT REGISTERS0LATCHRECEIVE DATA BUFFER WRSBUFRDD7D6D5D4D3D

9-4MAXQ610 User’s Guide9.1.2 USART Mode 1This mode provides asynchronous, full-duplex communication. A total of 10 bits is transmitted, consisting of

2-9MAXQ610 User’s Guide2.5.1 Memory Mapping Into Data SpaceThe MAXQ610 maps program memory into data space from 0000h to 7FFFh. The selec

9-5MAXQ610 User’s GuideFigure 9-2. USART Mode 1DIVIDEBY 4D7D6D5D4D3D2D1D001LOADCLOCKTRANSMIT SHIFT REGISTERS0LATCHRECEIVE DATA BUFFER WRSBUFRDD7D6D5D4

9-6MAXQ610 User’s GuideData is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples. Mode 2 uses the sample di

9-7MAXQ610 User’s Guide9.1.4 USART Mode 3This mode has the same operation as mode 2, except for the baud rate source. As shown in Figure 9-4, mode 3 g

9-8MAXQ610 User’s Guide9.2 Baud-Rate GenerationEach mode of operation has a baud-rate generator associated with it. The baud-rate generation technique

9-9MAXQ610 User’s GuideThe below formulas can be used to calculate the output of the baud-clock generator and the resultant mode 1, 3 baud rates. Addi

9-10MAXQ610 User’s GuideThe FE bit is set to a 1 when a framing error occurs. It must be cleared by software. Note that the FEDE state must be 1 while

9-11MAXQ610 User’s GuideBit 0: Receive Interrupt Flag (RI). This bit indicates that a data byte has been received in the serial port buffer. The bit i

10-1MAXQ610 User’s Guide10.1 SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10-2MAXQ610 User’s GuideSECTION 10: SERIAL PERIPHERAL INTERFACE (SPI) MODULEThe serial peripheral interface (SPI) module of the MAXQ610 microcontrolle

10-3MAXQ610 User’s Guidetransfer format. The polarity of the serial clock corresponds to the idle logic state of the clock line and therefore also def

2-10MAXQ610 User’s GuideFigure 2-4. CDA Functions in Word ModePHYSICAL DATAx0000x8000x4000DATA MEMORY015CDA1 = 0WORD MODE MEMORY MAP (UPA = 0, EXECUTI

10-4MAXQ610 User’s Guide10.2 SPI Slave SelectThe SPI slave-select SSEL can be configured to accept either an active-low or active-high SSEL signal thr

10-5MAXQ610 User’s GuideThe application software must correct the system conflict before resuming its normal operation. The MODF flag is set automatic

10-6MAXQ610 User’s Guidethe first clock edge or the active SSEL edge, dependent on the data transfer format. When SAS is cleared to 0, the active SSEL

10-7MAXQ610 User’s GuideBit 3: Mode Fault Flag (MODF). This bit is the mode fault flag for SPI master mode operation. When mode fault detec-tion is en

10-8MAXQ610 User’s Guide10.8.3 SPI Clock Register (SPICK)Bits 7:0: Clock Divider Ratio Bits 7:0 (CKR[7:0]). This 8-bit value determines the system

11-1MAXQ610 User’s Guide11.1 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11-2MAXQ610 User’s GuideSECTION 11: TEST ACCESS PORT (TAP)The MAXQ610 microcontroller incorporates a test access port (TAP) and TAP controller for com

11-3MAXQ610 User’s Guide11.2.2 Run-Test-IdleAs illustrated in Figure 11-1, the run-test-idle state is simply an intermediate state for getting to one

11-4MAXQ610 User’s GuideWhen the parallel instruction register (IR[2:0]) is updated, the TAP controller decodes the instruction and performs any neces

11-5MAXQ610 User’s GuideInstruction register (IR[2:0]) settings other than those listed and described above are reserved for internal use. As can be s

2-11MAXQ610 User’s GuideFigure 2-5. CDA Functions in Byte ModeUTILITY ROMPHYSICAL DATAx0000x8000xA000xFFFFx0000x7FFxFFFFDATA MEMORYPROGRAM MEMORY15 0

11-6MAXQ610 User’s GuideFor the host to establish a specific data communication link, a private instruction must be loaded into the IR[2:0] reg-ister.

11-7MAXQ610 User’s GuideFigure 11-4. TAP Controller Debug Mode DR-Scan ExampleOLD DATANEW DATADATA REGISTERTCKTMSTDITDOCONTROLSTATESHIFTREGISTERPARALL

12-1MAXQ610 User’s Guide12.1 Background Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12-2MAXQ610 User’s GuideSECTION 12: IN-CIRCUIT DEBUG MODEFlash-based MAXQ610 microcontroller devices are equipped with embedded debug hardware and emb

12-3MAXQ610 User’s GuideThe host now can transmit and receive serial data through the 10-bit data shift register that exists between the TDI input and

12-4MAXQ610 User’s GuideTable 12-1. Background Mode CommandsOP CODE COMMAND OPERATION0000–0000 No OperationNo operation (default state for debug shift

12-5MAXQ610 User’s Guide12.2 Breakpoint RegistersThe MAXQ610 microcontroller incorporates six breakpoint registers (BP0 to BP5) that are c

12-6MAXQ610 User’s Guideuser program. If an address match is detected, a break occurs, allowing the debug engine to take over control of the CPU and e

12-7MAXQ610 User’s Guide12.3 Debug ModeThere are two ways to enter the debug mode from background mode:• Issuance of the debug command directly by th

12-8MAXQ610 User’s Guidereloading the debug instruction. Once the debug engine has received the proper number of command and follow-on bytes for a giv

2-12MAXQ610 User’s Guide2.5.2 Memory Mapping into Code SpaceThe effective program address can be anywhere in the full 64KB memory space.

12-9MAXQ610 User’s Guide12.3.2 Read Register Map Command Host-Utility ROM InteractionA read register map command reads out data contents for all imple

12-10MAXQ610 User’s Guide12.3.3 Single-Step Operation (Trace)The debug engine supports single step operation in debug mode by executing a Trace comman

12-11MAXQ610 User’s Guide• Special caution should be exercised when using the write register command on register bits that globally

12-12MAXQ610 User’s GuideBit 5: Break-On Register Enable (REGE). The REGE bit is used to enable the break on register function. When REGE bit is set t

12-13MAXQ610 User’s Guide12.4.4 In-Circuit Debug Buffer Register (ICDB)This register serves as the parallel holding buffer for the debug shift registe

13-1MAXQ610 User’s Guide13.1 JTAG Bootloader Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13-2MAXQ610 User’s GuideSECTION 13: IN-SYSTEM PROGRAMMING (JTAG)Internal nonvolatile (flash) memory of MAXQ610 microcontrollers can be initia

13-3MAXQ610 User’s Guide13.2 Password-Protected AccessSome applications require preventive measures to protect against simple access and vi

14-1MAXQ610 User’s GuideSECTION 14: MAXQ610 INSTRUCTION SET SUMMARYTable 14-1. MAXQ610 Instruction Set SummaryMNEMONIC DESCRIPTION16-BIT INSTRUCTION W

14-2MAXQ610 User’s GuideTable 14-1. MAXQ610 Instruction Set Summary (continued)Note 1: The active accumulator (Acc) is not allowed as the src in oper

2-13MAXQ610 User’s Guide • When executing from the data memory (only when UPA is 0): Program flows freely between the lower 32KWords user code (P0

14-3MAXQ610 User’s GuideADD/ADDC src Add/Add with CarryDescription:The ADD instruction sums the active accumulator (Acc or A[AP]) and the specified sr

14-4MAXQ610 User’s GuideAND src Logical ANDDescription:Performs a logical-AND between the active accumulator (Acc) and the specified src data. For the

14-5MAXQ610 User’s Guide{L/S}CALL src {Long/Short} Call to SubroutineDescription:Performs a call to the subroutine destination specified by src. The C

14-6MAXQ610 User’s GuideCMP src Compare AccumulatorDescription:Compare for equality between the active accumulator and the least significant byte of t

14-7MAXQ610 User’s GuideEncoding:150f10n1101 ssss ssssExample(s):MOVE LC[1], #10h ; counter = 10hLoop:ADD @DP[0]++ ; add data memory contents to Acc,

14-8MAXQ610 User’s Guide{L/S} JUMP C/{L/S} JUMP NC, src {L/S} JUMP Z/{L/S} JUMP NZ, src{L/S} JUMP E/{L/S} JUMP NE, src{L/S} JUMP S, srcConditional {Lo

14-9MAXQ610 User’s GuideJUMP EOperation:E=1: IP ← IP + src (relative) –or— src (absolute)E=0: IP ← IP + 1Encoding:15000111100 ssss ssssExample(s):JUMP

14-10MAXQ610 User’s GuideTable 14-2. Source Specifier Codessrcsrc BIT ENCODINGf ssssssssWIDTH16 OR 8DESCRIPTION#k 0 kkkk kkkk 8 kkkkkkkk = Immediate (

14-11MAXQ610 User’s GuideTable 14-3. Destination Specifier Codesdstdst BIT ENCODINGddd ddddWIDTH16 OR 8DESCRIPTIONNUL 111 0110 8/16Null (Virtual) Dest

14-12MAXQ610 User’s GuideData Transfer Rulesdst (16-bit) ← src (16-bit): dst[15:0] ← src[15:0]dst (8-bit) ← src (8-bit): dst[7:0] ← src[7:0]dst (16-bi

2-14MAXQ610 User’s Guide2.6.1 Rules for System SoftwareWhile privilege levels are implemented in hardware, there are two ways user code could try to c

14-13MAXQ610 User’s GuideMOVE C, src.<b> Move Bit to Carry FlagDescription:Replaces the Carry (C) status flag with the specified source bit src.

14-14MAXQ610 User’s GuideMOVE dst.<b>, #1 Set BitDescription:Sets the bit specified by dst.<b>.Status Flags:C, E (if dst is PSF)Operation:

14-15MAXQ610 User’s GuideOR Acc.<b> Logical OR Carry Flag with Accumulator BitDescription:Performs a logical-OR between the Carry (C) status fla

14-16MAXQ610 User’s GuidePUSH src Push Word to the StackDescription:Increases the stack depth (decments the stack pointer SP) and pushes a single word

14-17MAXQ610 User’s GuideRET C/RET NC RET Z/RET NZRET SConditional Return on Status FlagDescription:Performs conditional return (RET) based upon the s

14-18MAXQ610 User’s GuideRET SOperation:S=1: IP ← @SP--S=0: IP ← IP + 1Encoding:1501100 1100 0000 1101Example(s):RET S ; S=0, return (RET) does not oc

14-19MAXQ610 User’s GuideRETI NCOperation:C=0: IP ← @SP--IPS ← 11bC=1: IP ← IP +1Encoding:1501110 1100 1000 1101Example(s):RETI NC ; C=1, return from

14-20MAXQ610 User’s GuideRL/RLCRotate Left Accumulator Carry Flag Exclusive/InclusiveDescription:Rotates the active accumulator left by a single bit p

14-21MAXQ610 User’s GuideRR/RRCRotate Right Accumulator Carry Flag Exclusive/InclusiveDescription:Rotates the active accumulator right by a single bit

14-22MAXQ610 User’s GuideSLA/SLA2/SLA4Shift Accumulator Left Arithmetically One, Two, or Four TimesDescription:Shifts the active accumulator left once

2-15MAXQ610 User’s Guide• A system library function that checks arguments before raising the privilege level must do so in an atomic fash-ion using

14-23MAXQ610 User’s GuideSR SRA/SRA2/SRA4Shift Accumulator Right Shift Accumulator Right Arithmetically One, Two, or Four TimesDescription:Shifts the

14-24MAXQ610 User’s GuideSRA4 Operation:15 Active Accumulator (Acc) 0 Carry Flag→ → →Acc.[11:0] ← Acc.[15:4]Acc.[15:12] ← Acc.15C ← Acc.3Encoding:1501

14-25MAXQ610 User’s GuideXCHExchange Accumulator BytesDescription:Exchanges the upper and lower bytes of the active accumulator.Status Flags:SOperatio

14-26MAXQ610 User’s GuideXOR Acc.<b> Logical XOR Carry Flag with Accumulator BitDescription:Performs a logical-XOR between the Carry (C) status

15-1MAXQ610 User’s Guide15.1 In-Application Programming Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15-2MAXQ610 User’s GuideSECTION 15: UTILITY ROMThe MAXQ610 utility ROM includes routines that provide the following functions to application software.

15-3MAXQ610 User’s Guide15.1 In-Application Programming Functions15.1.1 UROM_flashWriteNotes:• This function uses one stack level to save and restore

15-4MAXQ610 User’s Guide15.2 Data Transfer Functions15.2.1 UROM_moveDP0Notes:• Before calling this function, DPC should be set appropriately to confi

15-5MAXQ610 User’s Guide15.2.4 UROM_moveDP1Notes:• Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word

15-6MAXQ610 User’s Guide15.2.7 UROM_moveFPNotes:• Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or wor

iiMAXQ610 User’s GuideTABLE OF CONTENTSSECTION 1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-16MAXQ610 User’s GuideThis is no different for instructions that operate on data pointers. For example, a pointer to pointer move such as MOVE @DP[1

15-7MAXQ610 User’s Guide15.2.10 UROM_moveBPNotes:• Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or wo

15-8MAXQ610 User’s Guide15.4 ROM Example 1: Calling A Utility ROM Function DirectlyThis example shows the direct addressing method for calling utility

15-9MAXQ610 User’s Guide15.5 ROM Example 2: Calling A Utility ROM Function IndirectlyThe second example shows the indirect addressing method (

MAXQ610 User’s GuideREVISION HISTORYREVISION NUMBERREVISION DATESECTION NUMBERDESCRIPTIONPAGES CHANGED0 10/09 — Initial release —1 6/10 2Added Section

2-17MAXQ610 User’s GuideNext, the RAM routine calls into the flash function. Once we are executing out of flash, we can activate the DP[0] pointer wit

2-18MAXQ610 User’s GuideFigure 2-7 shows the code memory with passwords and the location of the values that are programmed into the ULDR/UAPP register

2-19MAXQ610 User’s GuideThere are two Family F loader commands specific to the MAXQ610: Command 0xF0: GetContext Input : None Output : Context Byte

2-20MAXQ610 User’s Guide2.6.8 Disabling MAXQ610-Specific Memory Access FeaturesThe MAXQ610 memory-protection features are specific to the MAXQ610/69 f

2-21MAXQ610 User’s Guide2.6.9 No User-Loader SegmentFor devices with only two memory segments, the user-loader memory region is excluded,

2-22MAXQ610 User’s Guide2.7 Clock GenerationAll functional modules in the MAXQ610 are synchronized to a single system clock with the exception of the

2-23MAXQ610 User’s Guide2.7.1 External Clock (Crystal/Resonator)An external quartz crystal or a ceramic resonator can be connected from HFXIN to HFXOU

2-24MAXQ610 User’s Guide2.7.3 Internal System Clock GenerationThe internal system clock is derived from the currently selected oscillator input. By de

2-25MAXQ610 User’s Guideis set, even if the interrupt source is disabled at the local or global level. Interrupt flags must be cleared within the user

1-1MAXQ610 User’s GuideSECTION 1: OVERVIEWThe MAXQM family of 16-bit reduced instruction set computing (RISC) microcontrollers is targeted towards low

2-26MAXQ610 User’s GuideExternal interrupts, when enabled, can be used as switchback sources from power-management mode. There is no latency associate

2-27MAXQ610 User’s Guide• Serial Port 0: assigned priority level 2• Timer B0: assigned priority level 2Because simultaneous interrupts are first eva

2-28MAXQ610 User’s Guide2.11.1 Power-On/Power-Fail ResetAn on-chip power-on reset (POR) circuit is provided to ensure proper initialization on interna

2-29MAXQ610 User’s GuidePOR level, a POR is generated. The power-fail monitor is enabled prior to the stop mode exit and before code execu-tion begins

2-30MAXQ610 User’s GuidePower-management mode is invoked by setting the PMME bit to 1. Once this bit has been set, one system clock cycle occurs every

2-31MAXQ610 User’s GuideNote that the voltage monitor and bandgap reference can be disabled during stop mode to conserve current consump-tion. In this

3-1MAXQ610 User’s Guide3.1 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2MAXQ610 User’s GuideLIST OF FIGURESFigure 3-1. Watchdog Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3MAXQ610 User’s GuideSECTION 3: PROGRAMMINGThis section provides a programming overview of the MAXQ610. For full details on the instruction set as w

3-4MAXQ610 User’s GuideHowever, the operation:move DP[0], #0055hdoes not require a prefixing operation even though the register DP[0] is

1-2MAXQ610 User’s GuidePeripheral registers (module 0 to module 5) on the MAXQ610 contain registers that are used to access the peripher-als, includin

3-5MAXQ610 User’s Guide3.3.4 Moving Values Between Registers of Different SizesBefore covering some transfer scenarios that might arise, a special reg

3-6MAXQ610 User’s Guide3.3.8 Low (16-Bit Destination) ← 8-Bit SourceTo modify only the low byte of a given 16-bit destination, the 16-bit register sho

3-7MAXQ610 User’s GuideRegister bits can be set or cleared individually using the MOVE instruction as follows:move IGE, #1 ; set IGE (Interrupt Glo

3-8MAXQ610 User’s Guide• SRA4 (Arithmetic shift right active accumulator 4 bit positions)• RL (Rotate active accumulator left)• RLC (

3-9MAXQ610 User’s Guide• Increment modulo 8: AP = AP[3] + ((AP[2:0] + 1) mod 8)• Decrement modulo 8: AP = AP[3] + ((AP[2:0] - 1) mod 8)• Incremen

3-10MAXQ610 User’s Guidesra ; Shift accumulator right arithmetically oncesra2 ; Shift accumulator right arithmetically twicesra4 ; S

3-11MAXQ610 User’s Guide3.6.2 Zero FlagThe zero flag (PSF.7) is a dynamic flag that reflects the current state of the active accumulator Acc. If all b

3-12MAXQ610 User’s Guide• MOVE Acc.<b>, C (Set selected active accumulator bit to carry)• AND Acc.<b> (Carry = carry AND selected act

3-13MAXQ610 User’s Guide3.7.3 Conditional JumpsConditional jumps transfer program execution based on the value of one of the status flags (C, E, Z, S)

3-14MAXQ610 User’s GuideWhen the supplied loop address is outside the relative jump range, the prefix register (PFX[0]) is used to supply the high byt

2-1MAXQ610 User’s GuideThis section contains the following information:SECTION 2: ARCHITECTURE2.1 Instruction Decoding . . . . . . . . . . . . . . . .

3-15MAXQ610 User’s Guide3.7.7 Conditional Return from InterruptSimilar to the conditional returns, the MAXQ610 microcontroller also supports a set of

3-16MAXQ610 User’s GuideBecause the stack is 16 bits wide, it is possible to store two 8-bit register values on it in a single location. This allows m

3-17MAXQ610 User’s Guidethe internal high-order bit that is used only for word-mode data-pointer access). Switching from byte- to word-access mode or

3-18MAXQ610 User’s Guidemove @++DP[1], @DP[1]--move @BP[++Offs], @BP[Offs--]move @--DP[0], @DP[0]++move @--DP[1], @DP[1]++move @BP[--Offs], @BP[Offs++

3-19MAXQ610 User’s GuideIf the timeout is reached without RWT being set, hardware generates a watchdog interrupt if the interrupt source has been enab

3-20MAXQ610 User’s GuideThe watchdog timeout selection is made using bits WD1 (WDCN.5) and WD0 (WDCN.4). The watchdog has four time-out selections bas

4-1MAXQ610 User’s Guide4.1 System Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-2MAXQ610 User’s GuideSECTION 4: SYSTEM REGISTER DESCRIPTIONRegisters currently defined in the MAXQ610 system register map are described in Tables 4-

4-3MAXQ610 User’s GuideTable 4-2. System Register Bit MapREGBIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0AP — — — — AP (4 bits)APC CLR IDS — — — MOD2 MOD1

4-4MAXQ610 User’s GuideTable 4-3. System Register Bit Reset ValuesNote 1: Bits marked as “s” are static across some or all resets.Note 2: ULDR/UAPP re

2-2MAXQ610 User’s GuideLIST OF FIGURESFigure 2-1. MAXQ610 Transport-Triggered Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-5MAXQ610 User’s Guide4.1 System Register DescriptionsThe addresses for each register are given in the format module[index], where module is the modu

4-6MAXQ610 User’s GuideREGISTER DESCRIPTIONPRIV, 08h[02h]Privilege Register (8 bits)InitializationThis register is reset to 00001111b on all resets.Bi

4-7MAXQ610 User’s GuideREGISTER DESCRIPTIONPSF, 08h[04h]Processor Status Flags Register (8 bits)InitializationThis register is cleared to 80h on all f

4-8MAXQ610 User’s GuideREGISTER DESCRIPTIONIC, 8h[5h]Interrupt and Control Register (8 bits)InitializationThis register is cleared to 0Ch on all forms

4-9MAXQ610 User’s GuideREGISTER DESCRIPTIONSC, 08h[08h]System Control Register (16 bits)InitializationThis register is reset to 000001ss100000s0b on a

4-10MAXQ610 User’s GuideREGISTER DESCRIPTIONSC.9 (PWLL) Password Lock User Loader. This bit defaults to 1 on power-fail and power-on reset. When this

4-11MAXQ610 User’s GuideREGISTER DESCRIPTIONPRIVF, 08h[0Bh]Privilege Flag Register (8 bits)InitializationThis register is cleared to 00h on all forms

4-12MAXQ610 User’s GuideREGISTER DESCRIPTIONCKCN, 08h[0Eh]System Clock Control Register (8 bits)InitializationBits 4:0 are cleared to zero on all form

4-13MAXQ610 User’s GuideREGISTER DESCRIPTIONWDCN, 08h[0Fh]Watchdog Control Register (8 bits)Initialization Bits 5, 4, 3, and 0 are cleared to 0 on all

4-14MAXQ610 User’s GuideREGISTER DESCRIPTIONWDCN.6 (EWDI) Watchdog Interrupt Enable. If this bit is set to 1, an interrupt request can be generated wh

2-3MAXQ610 User’s GuideSECTION 2: ARCHITECTUREThe MAXQ610 is designed to be modular and expandable. Top-level instruction decoding is extremely

4-15MAXQ610 User’s GuideREGISTER DESCRIPTIONIP, 0Ch[00h]Instruction Pointer Register (16 bits)InitializationThis register is cleared to 8000h on all f

4-16MAXQ610 User’s GuideREGISTER DESCRIPTIONDPC, 0Eh[04h]Data Pointer Control Register (16 bits)InitializationThis register is cleared to 005Ch on all

4-17MAXQ610 User’s GuideREGISTER DESCRIPTIONGRS, 0Eh[08h]General Register Byte-Swapped (16 bits)Initialization This register is cleared to 0000h on al

5-1MAXQ610 User’s Guide5.1 Peripheral Register Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-2MAXQ610 User’s GuideSECTION 5: PERIPHERAL REGISTER MODULESThe MAXQ610 microcontroller uses peripheral registers to control and monitor peripher

5-3MAXQ610 User’s GuideTable 5-3. Peripheral Register Reset ValuesTable 5-2. Peripheral Register Bit Function (continued)REGBIT15 14 13 12 11 10 9 8 7

5-4MAXQ610 User’s GuideTable 5-3. Peripheral Register Reset Values (continued)REGBIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0EIF1 0 0 0 0 0 0 0 0EIE1 0 0

5-5MAXQ610 User’s Guide5.1 Peripheral Register Bit DescriptionsREGISTER DESCRIPTIONPO0 (00h, 00h) Port 0 Output Register (8-bit register)Initializatio

5-6MAXQ610 User’s GuideREGISTER DESCRIPTIONEIF1 (06h, 00h) External Interrupt Flag 1 RegisterInitialization:EIF1 is cleared to 00h on all forms of res

5-7MAXQ610 User’s GuideREGISTER DESCRIPTIONPI3 (0Bh, 00h) Port 3 Input RegisterInitialization:The reset value for this register is dependent on the lo

2-4MAXQ610 User’s GuideMemory access from the MAXQ610 is based on a Harvard architecture with separate address spaces for program and data memory.

5-8MAXQ610 User’s GuideREGISTER DESCRIPTIONPD2 (12h, 00h) Port 2 Direction RegisterInitialization:This register is cleared to 00h on all resets except

5-9MAXQ610 User’s GuideREGISTER DESCRIPTIONWUTC (04h, 01h) Wake-Up Timer Control Register (8-bit register)Initialization:This register is cleared to 0

5-10MAXQ610 User’s GuideREGISTER DESCRIPTIONPWCN (0Ch, 01h) Power Control Register (16-bit register)Initialization:This register is set to 000000sss11

5-11MAXQ610 User’s GuideREGISTER DESCRIPTIONPWCN.5 (IRTXOUT) IRTX Output Pin Control. This bit controls the output drive state for the IRTX pin when t

5-12MAXQ610 User’s GuideREGISTER DESCRIPTIONTB0CN (01h, 02h) Timer B 0 Control Register (16-bit register)Initialization:This register is cleared to 00

5-13MAXQ610 User’s GuideREGISTER DESCRIPTIONTB0CN.5 (TBOE) Timer B Output Enable. Setting this bit to 1 enables the clock output function on the TBA p

5-14MAXQ610 User’s GuideREGISTER DESCRIPTIONIRCN (04h, 02h) Infrared Control Register (16-bit register)Initialization:This register is cleared to 0000

5-15MAXQ610 User’s GuideREGISTER DESCRIPTIONIRCN.12 to IRCN.10 (IRDIV[2:0]) IR Clock Divide Bits. These two bits select the divide ratio for the IR in

5-16MAXQ610 User’s GuideREGISTER DESCRIPTIONTB0C (08h, 02h) Timer B 0 Compare Register (16-bit register)Initialization:This register is cleared to 000

5-17MAXQ610 User’s GuideREGISTER DESCRIPTIONSCON0.6 (SM1)SCON0.7 (SM0/FE)Serial Port 0 Mode Bits 1:0 (when FEDE is 0). When FEDE is set to 1, this bit

2-5MAXQ610 User’s GuideThe MAXQ instruction set is designed to be highly orthogonal. All arithmetic and logical operations that use two reg-isters can

5-18MAXQ610 User’s GuideREGISTER DESCRIPTIONSCON1 (02h, 03h) Serial Port 1 Control Register Initialization:The serial port control is cleared to 00h o

5-19MAXQ610 User’s GuideREGISTER DESCRIPTIONSBUF1 (03h, 03h) Serial Data Buffer 1Initialization:This buffer is cleared to 00h on all forms of reset.Re

5-20MAXQ610 User’s GuideREGISTER DESCRIPTIONSMD0 (09h, 03h) Serial Port Mode Register 0Initialization:This register is cleared to 00h on all forms of

5-21MAXQ610 User’s GuideREGISTER DESCRIPTIONSPICF (0Ch, 03h) SPI Configuration RegisterInitialization:This buffer is cleared to 00h on all forms of re

6-1MAXQ610 User’s Guide6.1 Port Pin Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-2MAXQ610 User’s GuideSECTION 6: GENERAL-PURPOSE I/O MODULEThe MAXQ610 provides 38 port pins for general-purpose I/O that are grouped into eight port

6-3MAXQ610 User’s GuideAll these special functions are disabled by default with the exception of the JTAG interface pins, which are enabled by default

6-4MAXQ610 User’s GuideBits 7:0: Port 2 Output. This register stores the data that is output on any of the pins of port 2 that have been defined as ou

6-5MAXQ610 User’s GuideBits 7:0: Port 1 Input Bits. The read values of these bits reflect the logic states present at port 1 pins P1.0 to P1.7.Bits 7:

6-6MAXQ610 User’s GuideBits 7:0: Input/Output Direction for Port 0. The bits in this register control the input/output direction for port pins P0.0 to