MAXQ Family User’s Guide:
MAXQ2010 Supplement
14-4
14.4 RTC Register Descriptions
Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 15 decimal) and yy is the reg-
ister index (from 00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows:
• Name: Symbolic names of bits or bit fields in this register.
• Reset: The value of each bit in this register following a standard reset. If this field reads “unchanged,” the given bit
is unaffected by standard reset. If this field reads “s,” the given bit does not have a fixed 0 or 1 reset value because
its value is determined by another internal state or external condition.
• POR: If present this field defines the value of each bit in this register following a power-on reset (as opposed to a
standard reset). Some bits are unaffected by standard resets and are set/cleared by POR only.
• Access: Bits can be read-only (r) or read/write (rw). Any special restrictions or conditions that could apply when
reading or writing this bit are detailed in the bit description.
14.4.1 RTC Trim Register (RTRM, M0[18h])
Bit 7: RTC Trim Sign Bit (TSGN). This register bit selects whether 32K clocks are inserted (TSGN = 1) or removed
(TSGN = 0).
Bits 6:4: Reserved. Read returns zero.
Bits 3:0: RTC Trim Calibration Register (TRM[3:0]). These register bits provide a binary value between 00h to 0Fh,
which is used for adjusting 32K clocks insertion/removal. At every 10-second interval, a number of 32K clocks equal to
the RTRM[3:0] numeric value x 8 is inserted/removed from the RTC counter depending on the TSGN sign bit.
14.4.2 RTC Control Register (RCNT, M0[19h])
Note 1: This register is reset by power-on reset only.
Note 2: Write to this register is ignored when WE = 0 or RCNT.BUSY = 1.
Note 1: Bits 0 and 13 are reset by power-on reset only.
Note 2: Bits 14, 12:4, and 2:1 are reset by any reset source.
Note 3: Bit 3 is set to a 1 on system reset.
Note 4: Bit 0 is only writable when WE = 1 and BUSY = 0.
Note 5: Bit 13 is only writable when RTCE = 0.
Note 6: Bits 9:6 and 2:1 are only writable when BUSY = 0.
Bit #
7 6 5 4 3 2 1 0
Name TSGN — — — TRM
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Bit #
15 14 13 12 11 10 9 8
Name WE — ACS — — — FT SQE
Reset 0 1 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Bit #
7 6 5 4 3 2 1 0
Name ALSF ALDF RDYE RDY BUSY ASE ADE RTCE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw r rw rw rw
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