Maxim-integrated MAXQ7666 Manual do Utilizador descarregar pdf (Página 104)

3.2.8 Analog Interrupt Enable Register (AIE)

Bits 15 to 7 and 3: Reserved. Read returns 0, write ignored.

Bit 6: High-Frequency Oscillator Failure Interrupt Enable (HFFIE). See

Section 5

for details on this bit.

Bit 5: I/O Voltage Brownout Interrupt Enable (VIOBIE). See

Section 2

for details on this bit.

Bit 4: Digital Brownout Interrupt Enable (DVBIE). See

Section 2

for details on this bit.

Bit 2: ADC Overrun Interrupt Enable (AORIE). This bit must be set to logic 1 to generate an interrupt request when an ADC result

overrun occurs and the ADCOV flag is set to logic 1. Clearing this bit to 0 disables the interrupt capability from ADCOV. Note: To be

acknowledged by the microcontroller interrupt logic, this interrupt request must also be enabled by the IGE bit in the IC register and

IM5 mask in the IMR peripheral register.

Bit 1: ADC Data Ready Interrupt Enable (ADCIE). This bit must be set to logic 1 to generate an interrupt request when the ADC com-

pletes a conversion and the ADCRY flag is set to logic 1. Clearing this bit to 0 disables the interrupt capability from ADCRY. Note: To

be acknowledged by the microcontroller interrupt logic, this interrupt request must also be enabled by the IGE bit in the IC register

and IM5 mask in the IMR peripheral register.

Bit 0: This bit is implemented and available to be used as a user-software-controlled bit.

MAXQ7665/MAXQ7666 User’s Guide

3-14

Bit #

15 14 13 12 11 10 9 8

Name — — — — — — — —

Reset 0 0 0 0 0 0 0 0

Access r r r r r r r r

Bit #

7 6 5 4 3 2 1 0

Name — HFFIE VIOBIE DVBIE — AORIE ADCIE —

Reset 0 0 0 0 0 0 0 1

Access r rw rw rw r rw rw rw

r = read, w = write

Note: This register is cleared to 0001h on all forms of reset.

Maxim Integrated

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Maxim-integrated MAXQ7666 Manual do Utilizador Página 104