Maxim-integrated MAXQ7666 Manual do Utilizador descarregar pdf (Página 280)

9.2.3 SPI Configuration Register (SPICF)

Bits 15 to 8, 6 to 3: Reserved. Read 0, write ignored.

Bit 7: Enable SPI Interrupt (ESPII). This bit enables any of the SPI interrupt source flags (MODF, WCOL, ROVR, SPIC) to generate

interrupt requests. Note: For interrupt requests to happen, global interrupt mask bits IM1 (in the IMR register) and IGE (in the IC periph-

eral register) must also be enabled.

0 = SPI interrupt sources disabled.

1 = SPI interrupt sources enabled.

Bit 2: Character Length Select (CHR). This bit determines the character length for an SPI transfer cycle. A character can be 8 bits in

length or 16 bits in length.

0 = 8-bit character length specified.

1 = 16-bit character length specified.

Bit 1: Clock Phase Select (CKPHA). This bit selects the clock phase and is used with the CKPOL bit to define the SPI data transfer

format.

0 = Data sampled on the active clock edge.

1 = Data sampled on the inactive clock edge.

Bit 0: Clock Polarity Select (CKPOL). This bit selects the clock polarity and is used with the CKPHA bit to define the SPI data trans-

fer format.

0 = Clock idles in the logic 0 state (rising = active clock edge).

1 = Clock idles in the logic 1 state (falling = active clock edge).

MAXQ7665/MAXQ7666 User’s Guide

9-7

Bit #

15 14 13 12 11 10 9 8

Name — — — — — — — —

Reset 0 0 0 0 0 0 0 0

Access r r r r r r r r

Bit #

76543210

Name ESPII — — — — CHR CKPHA CKPOL

Reset 0 0 0 0 0 0 0 0

Access rw r r r r rw rw rw

r = read, w = write

Maxim Integrated

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Maxim-integrated MAXQ7666 Manual do Utilizador Página 280