Maxim-integrated MAX31782 Manual do Utilizador Página 139

  • Descarregar
  • Adicionar aos meus manuais
  • Imprimir
  • Página
    / 223
  • Índice
  • MARCADORES
  • Avaliado. / 5. Com base em avaliações de clientes
Vista de página 138
Maxim Integrated 17-4
MAX31782 User’s Guide
Revision 0; 8/11
Table 17-2. Background Mode Commands (continued)
OP CODE COMMAND OPERATION
0000–0011 Read ICDA
Read data from the ICDA. The contents of the ICDA register are loaded into the debug shift reg-
ister through the ICDB register for host read. This command requires two follow-on transfer cycles
with the least significant byte first.
0000–0100 Read ICDD
Read data from the ICDD. The contents of the ICDD register are loaded into the debug shift reg-
ister through the ICDB register for host read. This command requires two follow-on transfer cycles
with the least significant byte first.
0000–0101 Read BP0
Read data from the BP0.The contents of the BP0 register are loaded into the debug shift register
through the ICDB register for host read. This command requires two follow-on transfer cycles with
the least significant byte first.
0000–0110 Read BP1
Read data from the BP1. The contents of the BP1 register are loaded into the debug shift register
through the ICDB register for host read. This command requires two follow-on transfer cycles with
the least significant byte first.
0000–0111 Read BP2
Read data from the BP2. The contents of the BP2 register are loaded into the debug shift register
through the ICDB register for host read. This command requires two follow-on transfer cycles with
the least significant byte first.
0000–1000 Read BP3
Read data from the BP3. The contents of the BP3 register are loaded into the debug shift register
through the ICDB register for host read. This command requires two follow-on transfer cycles with
the least significant byte first.
0000–1001 Read BP4
Read data from the BP4. The contents of the BP4 register are loaded into the debug shift register
via the ICDB register for host read. This command requires two follow-on transfer cycles with the
least significant byte first.
0000–1010 Read BP5
Read data from the BP5. The contents of the BP5 register are loaded into the debug shift register
via the ICDB register for host read. This command requires two follow-on transfer cycles with the
least significant byte first.
0001–0001 Write ICDC
Write control data to the ICDC. The contents of ICDB are loaded into the ICDC register by the
debug engine at the end of the data transfer cycle.
0001–0011 Write ICDA
Write data to the ICDA. The contents of ICDB are loaded into the ICDA register by the debug
engine at the end of the data transfer cycles. Data is transferred with the least significant byte first.
0001–0100 Write ICDD
Write data to the ICDD. The contents of ICDB are loaded into the ICDD register by the debug
engine at the end of data transfer cycles. Data is transferred with the least significant byte first.
0001–0101 Write BP0
Write data to the BP0. The contents of ICDB are loaded into the BP0 register by the debug
engine at the end of data transfer cycles. Data is transferred with the least significant byte first.
0001–0110 Write BP1
Write data to the BP1. The contents of ICDB are loaded into the BP1 register by the debug
engine at the end of data transfer cycles. Data is transferred with the least significant byte first.
0001–0111 Write BP2
Write data to the BP2. The contents of ICDB are loaded into the BP2 register by the debug
engine at the end of data transfer cycles. Data is transferred with the least significant byte first.
0001–1000 Write BP3
Write data to the BP3. The contents of ICDB are loaded into the BP3 register by the debug
engine at the end of data transfer cycles. Data is transferred with the least significant byte first.
0001–1001 Write BP4
Write data to the BP4. The contents of ICDB are loaded into the BP4 register by the debug
engine at the end of data transfer cycles. Data is transferred with the least significant byte first.
0001–1010 Write BP5
Write data to the BP5. The contents of ICDB are loaded into the BP5 register by the debug
engine at the end of data transfer cycles. Data is transferred with the least significant byte first.
0001–1111 Debug
Debug command. This command forces the debug engine into debug mode and halts the CPU
operation at the completion of the current instruction after the debug command is recognized by
the debug engine.
Vista de página 138
1 2 ... 134 135 136 137 138 139 140 141 142 143 144 ... 222 223

Comentários a estes Manuais

Sem comentários