Maxim Integrated 11-4
MAX31782 User’s Guide
Revision 0; 8/11
11.1 GPIO Port 1 Register Descriptions
Port 1 provides six GPIO pins that are multiplexed with PWM functionality. The PWM function is enabled when either the
PWMCNn.PWMCR or PWMCS bits are a 1, where n = 0 to 5. If both of these bits are a 0, the pin operates as a GPIO.
The port 1 pins provide all the functionality shown in the GPIO block diagram (Figure 11-1). This port does not provide
GPIO interrupts.
11.1.1 GPIO Direction Register Port 1 (PD1)
PD1 is an 8-bit register used to determine the direction of the pins when they are used as GPIO pins. Each pin is inde-
pendently controlled by its direction bit. When PD1.n (n = 0 to 5) is set to 1, the pin is an output; data in the PO1.n bit
is driven on the pin. When PD1.n is cleared to 0, the pin is an input, and allows an external signal to drive the pin. Note
that each port pin has a weak pullup circuit when functioning as an input. The p-channel pullup transistor is controlled
by the PO1.n bit. If PO1.n is set to 1, the corresponding weak pullup is turned on; if the PO1.n bit is cleared to 0, the
weak pullup is turned off and the pin’s input is high impedance. When the port 1 pins are operating as PWM pins, the
data in PD1 does not affect PWM operation.
11.1.2 GPIO Output Register Port 1 (PO1)
PO1 is an 8-bit register that controls the output data of a GPIO pin. If the pin is setup to be an output (PD1.n = 1), the
data in PO1.n is output on the pin. If the pin is set as an input (PD1.n = 0), setting PO1.n to a 1 enables a p-channel
weak pullup, otherwise the pin’s input is high impedance. When the port 1 pins are operating as PWM pins, the data
in PO1 does not affect PWM operation. Changing the direction of the pin does not change the data content of PO1.n.
11.1.3 GPIO Input Register for Port 1 (PI1)
PI1 is an 8-bit register that contains the data that is applied to the GPIO pins. The PI1 input register contains valid input
data even when the pin is not operating as a GPIO. The reset value for this register is dependent on the logical states
applied to the pins. Note that each pin has a weak pullup circuit when functioning as an input and the p-channel pullup
transistor is controlled by the PO1.n bit.
Bit
7 6 5 4 3 2 1 0
Name — — PD1_5 PD1_4 PD1_3 PD1_2 PD1_1 PD1_0
Reset 0 0 0 0 0 0 0 0
Access r r rw rw rw rw rw rw
Bit
7 6 5 4 3 2 1 0
Name — — PO1_5 PO1_4 PO1_3 PO1_2 PO1_1 PO1_0
Reset 1 1 1 1 1 1 1 1
Access r r rw rw rw rw rw rw
Bit
7 6 5 4 3 2 1 0
Name — — PI1_5 PI1_4 PI1_3 PI1_2 PI1_1 PI1_0
Reset 1 1 s s s s s s
Access r r r r r r r r
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