Maxim Integrated 17-5
MAX31782 User’s Guide
Revision 0; 8/11
17.1.1 Breakpoint Registers
The MAX31782 incorporates six breakpoint registers (BP0–BP5) that are configurable by the host for establishing different
types of breakpoint mechanisms. The first four breakpoint registers (BP0–BP3) are 16-bit registers that are configurable
as program memory address breakpoints. When enabled, the debug engine forces a break when a match between the
breakpoint register and the program memory execution address occurs. The final two 16-bit breakpoint registers (BP4, BP5)
are configurable in one of two possible capacities. They may be configured as data memory address breakpoints or may
be configured to support register access breakpoints. In either case, if breakpoints are enabled and the defined breakpoint
match occurs, the debug engine generates a break condition. The six breakpoint registers are documented below.
17.1.1.1 Breakpoint 0 Register (BP0)
The breakpoint 0 register is accessible only through background mode read/write commands. Breakpoint registers
BP0, BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the
debug engine monitors the program-address bus activity while the CPU is executing the user program. If an address
match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
17.1.1.2 Breakpoint 1 Register (BP1)
The breakpoint 1 register is accessible only via background mode read/write commands. Breakpoint registers BP0,
BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the
debug engine monitors the program-address bus activity while the CPU is executing the user program. If an address
match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
17.1.1.3 Breakpoint 2 Register (BP2)
The breakpoint 2 register is accessible only via background mode read/write commands. Breakpoint registers BP0,
BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the
debug engine monitors the program-address bus activity while the CPU is executing the user program. If an address
match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
s = special
s = special
s = special
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BP0.15 BP0.14 BP0.13 BP0.12 BP0.11 BP0.10 BP0.9 BP0.8 BP0.7 BP0.6 BP0.5 BP0.4 BP0.3 BP0.2 BP0.1 BP0.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s s s s s s s s s
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
BP1.15 BP1.14 BP1.13 BP1.12 BP1.11 BP1.10 BP1.9 BP1.8 BP1.7 BP1.6 BP1.5 BP1.4 BP1.3 BP1.2 BP1.1 BP1.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s s s s s s s s s
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BP2.15 BP2.14 BP2.13 BP2.12 BP2.11 BP2.10 BP2.9 BP2.8 BP2.7 BP2.6 BP2.5 BP2.4 BP2.3 BP2.2 BP2.1 BP2.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s s s s s s s s s
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