
Maxim Integrated 8-13
MAX31782 User’s Guide
Revision 0; 8/11
8.2.8 SMBus Mode Selection Register (SMBUS)
Address: M3[04h]
This register contains bits that are used for both the I
2
C slave interface (SDA and SCL) and the I
2
C master interface
(MSDA and MSCL). For operation of the master interface, only the master bits should be used.
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name —
— — — — — — — — — — —
RESET_S RESET_M SMB_MOD_S SMB_MOD_M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access r r r r r r r r r r r r rw rw rw rw
BIT NAME DESCRIPTION
15:4 —
Reserved. The user should not write to these bits.
3 RESET_S This bit does not affect the master I
2
C interface (MSDA and MSCL).
2 RESET_M
I
2
C Master Reset Bit. This bit can be used by the software to unconditionally reset and disable the
I
2
C master interface. After at least one system clock cycle, this bit must be cleared by software.
After this bit is toggled, all the relevant I
2
C master registers need to be reinitialized.
1 SMB_MOD_S This bit does not affect the master I
2
C interface (MSDA and MSCL).
0 SMB_MOD_M
This bit enables the SMBUS timeout feature only when the master I
2
C interface (MSDA and MSCL)
is enabled to be a slave interface. See the 8.1.12 Operation as a Slave section for more details.
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