Maxim Integrated 17-6
MAX31782 User’s Guide
Revision 0; 8/11
17.1.1.4 Breakpoint 3 Register (BP3)
The breakpoint 3 register is accessible only via background mode read/write commands. Breakpoint registers BP0,
BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the
debug engine monitors the program-address bus activity while the CPU is executing the user program. If an address
match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
17.1.1.5 Breakpoint 4 Register (BP4)
The breakpoint 4 register is accessible only via background mode read/write commands.
When REGE = 0: This register serves as one of the two data memory address breakpoints. When DME is set in back-
ground mode, the debug engine monitors the data memory address bus activity while the CPU is executing the user
program. If an address match is detected, a break occurs, allowing the debug engine to take over control of the CPU
and enter debug mode.
When REGE = 1: This register serves as one of the two register breakpoints. A break occurs when the destination
register address for the executed instruction matches with the specified module and index. The destination module is
indicated by the M[3:0] bits and the register within that module is defined by the R[4:0] bits.
17.1.1.6 Breakpoint 5 Register (BP5)
The breakpoint 5 register is accessible only via background mode read/write commands.
When REGE = 0: This register serves as one of the two data memory address breakpoints. When DME is set in back-
ground mode, the debug engine monitors the data memory address bus activity while the CPU is executing the user
program. If an address match is detected, a break occurs, allowing the debug engine to take over control of the CPU
and enter debug mode.
s = special
s = special
s = special
s = special
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BP3.15 BP3.14 BP3.13 BP3.12 BP3.11 BP3.10 BP3.9 BP3.8 BP3.7 BP3.6 BP3.5 BP3.4 BP3.3 BP3.2 BP3.1 BP3.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s s s s s s s s s
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BP4.15 BP4.14 BP4.13 BP4.12 BP4.11 BP4.10 BP4.9 BP4.8 BP4.7 BP4.6 BP4.5 BP4.4 BP4.3 BP4.2 BP4.1 BP4.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s s s s s s s s s
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name - - - - - - - R.4 R.3 R.2 R.1 R.0 M.3 M.2 M.1 M.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s s s s s s s s s
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BP5.15 BP5.14 BP5.13 BP5.12 BP5.11 BP5.10 BP5.9 BP5.8 BP5.7 BP5.6 BP5.5 BP5.4 BP5.3 BP5.2 BP5.1 BP5.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s* s* s* s* s* s** s** s** s**
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