MAXQ612/MAXQ622 User’s Guide
Maxim Integrated 5-29
REGISTER DESCRIPTION
I2CCK (08h, 04h) I
2
C Clock Control Register (16-bit register)
Initialization: This register is set to 0204h on all forms of reset.
Read/Write Access: Unrestricted read. Writes to this register are allowed only when I2CBUSY = 0. This register
has no function when operating in slave mode and the clock generation circuitry should be
disabled.
I2CCK.7 to I2CCK.0 (I2CCKL[7:0]) I
2
C Clock Low Bits 7:0. These bits define the I
2
C SCL low period in number of system
clock, with bit 7 as the most significant bit. The duration of SCL low time is calculated using
the following equation:
I
2
C Low Time Period = System Clock x (I2CCKL[7:0] + 1)
When operating in master mode, the I2CCKL must be set to a minimum value of 4 to ensure
proper operation. Any value less than 4 is set to 4.
I2CCK.15 to I2CCK.8
(I2CCKH[7:0])
I
2
C Clock High Bits 7:0. These bits define the I
2
C SCL high period in number of system
clock, with bit 7 as the most significant bit. The duration of SCL high time is calculated
using the following equation:
I
2
C High Time Period = System Clock x (I2CCKH[7:0] + 1)
When operating in master mode, the I2CCKH must be set to a minimum value of 2 to ensure
proper operation. Any value less than 2 is set to 2.
I2CTO (09h, 04h) I
2
C Timeout Register (8-bit register)
Initialization: This register is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write access.
I2CTO.7 to I2CTO.0 I
2
C Timeout Register Bits 7:0. This register is used only in master mode. This register
determines the number of I
2
C Bit Period (SCL High + SCL Low) the I
2
C master waits for
SCL to go high. The timeout timer resets to 0 and starts to count after the I2CSTART bit is
set or every time the SCL goes low. When cleared to 00h, the timeout function is disabled
and the I
2
C waits for SCL to go high indefinitely during a transmission. When set to any
other values, the I
2
C waits until the timeout expires and sets the I2CTOI flag.
I2C Timeout = I2C Bit Rate x (I2CTO[7:0] + 1)
Note that these bits have no effect when the I2C module is operating in slave mode
(I2CMST = 0). When operating in slave mode, SCL is controlled by an external master.
I2CSLA (0Ah, 04h) I
2
C Slave Address Register (16-bit register)
Initialization: This register is cleared to 0000h on all forms of reset.
Read/Write Access: Unrestricted read/write access.
I2CSLA.9 to I2CSLA.0 I
2
C Slave Address Register Bits 9:0. These address bits contain the address of the
I
2
C device. When a match to this address is detected, the I
2
C controller automatically
acknowledges the transmitter with the I2CACK bit value if the I
2
C module is enabled
(I2CEN = 1). The I2CAMI flag is set to 1 and the I2CMST bit is cleared to 0. An interrupt is
generated to the CPU if enabled.
I2CSLA.15 to I2CSLA.10
Reserved. Reads return 0.
(93 páginas)
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentários a estes Manuais