MAXQ612/MAXQ622 User’s Guide
Maxim Integrated 11-1
11.1 I
2
C Mode of Operation....................................................................11-2
11.1.1 Master-Transmitter ..................................................................11-2
11.1.2 Master-Receiver .......................................................................11-4
11.1.3 Slave-Transmitter ...................................................................11-4
11.1.4 Slave-Receiver .....................................................................11-6
11.2 I
2
C Clock Generation.....................................................................11-6
11.3 I
2
C Controller Reset ......................................................................11-7
11.4 I
2
C Peripheral Register Descriptions.........................................................11-8
11.4.1 I
2
C Control Register (I2CCN)..........................................................11-8
11.4.2 I
2
C Status Register (I2CST) ...........................................................11-9
11.4.3 I
2
C Data Buffer Register (I2CBUF) .....................................................11-10
11.4.4 I
2
C Interrupt Enable Register (I2CIE) ...................................................11-11
11.4.5 I
2
C Clock Control Register (I2CCK).....................................................11-12
11.4.6 I
2
C Timeout Register (I2CTO) .........................................................11-12
11.4.7 I
2
C Slave Address Register (I2CSLA) ...................................................11-13
11.5 I
2
C Examples ...........................................................................11-13
11.5.1 I
2
C Example: Master Mode, Transmit ...................................................11-13
11.5.2 I
2
C Example: Master Mode, Receive....................................................11-14
11.5.3 I
2
C Example: Slave Mode, Receive.....................................................11-14
11.5.4 I
2
C Example: Slave Mode, Transmit ....................................................11-15
SECTION 11: I
2
C INTERFACE
This section contains the following information:
LIST OF FIGURES
Figure 11-1. Roles of I
2
C Devices and Direction of I
2
C Signals ........................................11-2
Figure 11-2. I
2
C Master-Transmitter Data Transfer ..................................................11-3
Figure 11-3. I
2
C Master-Transmitter and Master-Receiver ............................................11-3
Figure 11-4. I
2
C Master-Receiver Data Transfer ....................................................11-4
Figure 11-5. I
2
C Slave Transmitter and Slave Receiver ..............................................11-5
Figure 11-6. I
2
C Clock Period ..................................................................11-6
LIST OF TABLES
Table 11-1. Definition of I
2
C Bus Terminology .....................................................11-2
Table 11-2. Sample I
2
C Clock Setting for 50ns Rise/Fall Time .........................................11-7
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