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MAXQ612/MAXQ622 User’s Guide

2-30 Maxim Integrated

The MAXQ612/MAXQ622 support power-fail detection where an on-chip bandgap and reference comparator constant-

ly monitor the supply voltage V

to ensure that it is within acceptable limits. If V

is below the power-fail level warn-

ing level, an interrupt is generated to the CPU if enabled. If V

falls further to below the operating condition, the power

monitor initiates a reset condition. This can occur either when the MAXQ612/MAXQ622 are first powered up when the

supply is above the POR voltage threshold, or when V

drops out of tolerance from an acceptable level.

In either case, the reset condition is maintained until V

rises above the reset level V

RST

. Once (V

> V

RST

), there

is a delay of 8192 oscillator cycles until execution resumes to ensure that the clock source has stabilized.

Rather than leaving the power-fail reset monitoring circuit always on once the V

RST

condition has occurred, it can be

advantageous to the application to conserve battery capacity during power-fail reset in order to extend the time until

POR is reached (and possibly retaining SRAM contents). While there is still no single bit indicator that can be used to

guarantee SRAM retention once power-fail reset has occurred, one possibility is that the user can perform a checksum

over the area for which retention is questioned to make this assessment. So, in order to reduce current consumption

during the power-fail reset state, two power-fail reset check time configuration bits (PFRCK[1:0]) are provided for the

user. These bits are used to enable duty cycling of the V

RST

power-monitoring circuitry during the time when V

below the V

RST

threshold but has not reached the POR threshold. These bits are reset only by POR (not even V

RST

Table 2-9 provides the bit settings and corresponding duty cycling of the power monitor check when V

POR

< V

RST

. Note that the V

POR

state for the bits is 00b, which results in the monitor being on always.

During the power-fail reset condition, duty cycling of the V

RST

power-monitoring circuitry results in reduced current that

can be approximated by the following equation:

POWERFAIL

= (3 x I

+ (Check Interval Cycles - 3) x (I

+ I

NANO

))/Check Interval Cycles

where:

= stop-mode current with power-fail monitor off

= stop-mode current with power-fail monitor on

NANO

= nanopower ring oscillator current

When the processor exits from the power-on/power-fail reset state, the POR bit in the watchdog control register

(WDCN) is set to 1 and can only be cleared by software. The user software can examine the POR bit following a reset

to determine whether the reset was caused by a power-on reset or by another source.

The power-fail monitor is always on during normal operation. However, it can be selectively disabled during stop

mode using the power-fail monitor disable (PFD) bit in the PWCN register if the regulator is also selectively disabled

(REGEN = 0) during stop mode. If the user opts to leave the regulator on during stop mode, the power-fail monitor is

automatically left enabled as well, regardless of the state of the PFD bit. The reset default state for the PFD bit is 0,

which enables the power-fail monitor function during stop mode. If power-fail monitoring is disabled (PFD = 1) during

stop mode, the circuitry responsible for generating a power-fail warning or reset is shut down and neither condition is

detected. Thus, the V

< V

RST

condition does not generate a reset. However, in the event that V

falls below the

POR level, a POR is generated. The power-fail monitor is enabled prior to the stop mode exit and before code execu-

tion begins. If a power-fail warning condition (V

< V

PFW

) is then detected, the power-fail interrupt flag is set on stop

mode exit. If a power-fail reset condition is detected (V

< V

RST

), the CPU goes into reset.

2.11.2 External Reset

During normal operation, the MAXQ612/MAXQ622 are placed into external reset mode by holding the RESET pin low

for at least four clock cycles. If the MAXQ612/MAXQ622 are in the low-power stop mode (i.e., system clock is not

active), the RESET pin becomes an asynchronous source, forcing the reset state immediately after being taken low.

Once the MAXQ612/MAXQ622 enter reset mode, it remains in reset as long as the RESET pin is held low. After the

RESET pin returns to high, the processor exits the reset state within four clock cycles and begins program execution

from utility ROM at address 8000h.

The RESET pin is an output as well as an input. If a reset condition is caused by another source (such as a power-fail

reset or internal reset), an output reset pulse is generated at the RESET pin for as long as the MAXQ612/MAXQ622

remain in reset. If the RESET pin is connected to an RC reset circuit or a similar circuit, it may not be able to drive the

output reset signal; however, if this occurs, it does not affect the internal reset condition.

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