Maxim-integrated MAXQ622 Manual do Utilizador descarregar pdf (Página 165)

MAXQ612/MAXQ622 User’s Guide

11-10 Maxim Integrated

Bit 9: I

C Receiver Overrun Flag (I2CROI). This bit indicates a receive overrun when set to 1. This bit is set to 1 if the

receiver has already received 2 bytes since the last CPU read. This bit is cleared to 0 by software reading the I2CBUF.

Setting this bit to 1 by software causes an interrupt if enabled. Writing 0 to this bit does not clear the interrupt.

Bit 8: I

C General Call Interrupt Flag (I2CGCI). This bit is set to 1 when the general call is enabled (I2CGCEN = 1)

and the general call address is received. This bit must be cleared to 0 by software once set. Setting this bit to 1 by

software causes an interrupt if enabled.

Bit 7: I

C NACK Interrupt Flag (I2CNACKI). This bit is set to 1 if the I

C transmitter receives a NACK from the receiver.

Setting this bit to 1 by hardware causes an interrupt if enabled. This bit must be cleared to 0 by software once set.

This bit is set by hardware only

Bit 6: I

C Arbitration Loss Flag (I2CALI). This bit is set to 1 when the I

C is configured as a master and loses in the

arbitration. When the master loses arbitration, the I2CMST bit is cleared to 0. Setting this bit to 1 by hardware causes

an interrupt if enabled. This bit must be cleared to 0 by software once set. This bit is set by hardware only.

Bit 5: I

C Slave Address Match Interrupt Flag (I2CAMI). This bit is set to 1 when the I

C controller receives an

address that matches the contents in its slave address register (I2CSLA) during the address stage. This bit must be

cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if enabled.

Bit 4: I

C Timeout Interrupt Flag (I2CTOI). This bit is set to 1 if either the I

C controller cannot generate a START

condition or the I

C SCL low time has expired the timeout value specified in I2CTO register. This happens when the

C controller is operating in master mode and some other device on the bus is using the bus or holding SCL low for

an extended period of time. This bit must be cleared to 0 by software once set. Setting this bit to 1 by software causes

an interrupt if enabled.

Bit 3: I

C Clock Stretch Interrupt Flag (I2CSTRI). This bit indicates that the I

C controller is operating with clock

stretching enabled and is holding the SCL clock signal low. The I

C controller releases SCL after this bit has been

cleared to 0. Setting this bit to 1 by hardware causes an interrupt if enabled. This bit must be cleared to 0 by software

once set. This bit is set by hardware only.

Bit 2: I

C Receive Ready Interrupt Flag (I2CRXI). This bit indicates that a data byte has been received in the I

buffer. This bit must be cleared by software once set. Setting this bit to 1 by hardware causes an interrupt if enabled.

This bit is set by hardware only.

Bit 1: I

C Transmit Complete Interrupt Flag (I2CTXI). This bit indicates that an address or a data byte has been suc-

cessfully shifted out and the I

C controller has received an acknowledgment from the receiver (NACK or ACK). This bit

must be cleared by software once set. Setting this bit to 1 by software causes an interrupt if enabled.

Bit 0: I

C START Interrupt Flag (I2CSRI). This bit is set to 1 when a START condition (S or Sr) is detected. This bit

must be cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if enabled.

11.4.3 I

C Data Buffer Register (I2CBUF)

C Data Read and Write: Data for I

C transfer is read and written to this location. The I

C transmit and receive buffers

are internally stored separately, however, both are accessed through this buffer.

C Address Transmission: When transmitting an I

C address, the address should be loaded into I2CBUF[6:0].

I2CBUF[7] is ignored and is not part of the I

C address.

I2CBUF

C Data Buffer Register

M4[02h]

Bit # 7 6 5 4 3 2 1 0

Name I2CBUF7 I2CBUF6 I2CBUF5 I2CBUF4 I2CBUF3 I2CBUF2 I2CBUF1 I2CBUF0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw rw rw rw rw

1 2 ... 160 161 162 163 164 165 166 167 168 169 170 ... 254 255

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