Maxim-integrated MAXQ622 Manual do Utilizador descarregar pdf (Página 183)

MAXQ612/MAXQ622 User’s Guide

Maxim Integrated 12-13

12.4.14 Endpoint 3 IN Byte Count Register (EP3BC)

Bit 7: Reserved. Reads returns zero.

Bits 6 to 0: EP3-IN Byte Count. This register contains the number of bytes the CPU has loaded into EP3 buffer for the

next IN transfer. Writing to the EP3BC register arms endpoint 3 for the next IN transfer.

12.4.15 Endpoint 0 Buffer Register (EP0BUF)

Bits 7 to 0: EP0 Buffer (EP0BUF[7:0]). These data register bits are used for reading/supplying data to the 64-byte

EP0 buffer for OUT and IN transfers to and from the bidirectional endpoint 0.

For an IN transfer, the CPU writes a series of bytes to this EP0BUF to fill it with IN data. After filling the buffer with a

packet (0 to 64 bytes), the CPU writes the byte count register (EP0BC) to arm the IN transfer and to tell the SIE how

many bytes to transfer when it receives the IN packet to EP0.

For an OUT transfer, the SIE fills the buffer with USB data received from the host. When the OUT transfer is verified to

be error-free, the SIE loads the byte count register (EP0BC) to indicate the number of bytes received in the OUT data

transfer. For a successful transfer the SIE also ACKs the OUT transfer and asserts the OUT0DAV interrupt request bit.

Note: This register is indetermistic on POR and retains its value on all other forms of reset.

EP3BC

Endpoint 3 IN Byte Count Register

UADDR[4:0] = 0Eh

EP0BUF

Endpoint 0 Buffer Register

UADDR[4:0] = 10h

Bit # 7 6 5 4 3 2 1 0

Name — EP3BC6 EP3BC5 EP3BC4 EP3BC3 EP3BC2 EP3BC1 EP3BC0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw rw rw rw rw

Bit # 7 6 5 4 3 2 1 0

Name EP0BUF7 EP0BUF6 EP0BUF5 EP0BUF4 EP0BUF3 EP0BUF2 EP0BUF1 EP0BUF0

Reset s s s s s s s s

Access rw rw rw rw rw rw rw rw

1 2 ... 178 179 180 181 182 183 184 185 186 187 188 ... 254 255

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Maxim-integrated MAXQ622 Manual do Utilizador Página 183