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MAXQ612/MAXQ622 User’s Guide

16-2 Maxim Integrated

Table 16-1. MAXQ612/MAXQ622 Instruction Set Summary (continued)

Note 1: The active accumulator (Acc) is not allowed as the src in operations where it is the implicit destination.

Note 2: The CPU stalls when code is executed from flash with the destination being an IP register or when the code pointer is

used. This stall requires two execution cycles to complete the instruction.

Note 3: Only module 8 and modules 0 to 5 (when implemented for a given product) are supported by these single-cycle bit opera-

tions. Potentially affects C or E if PSF register is the destination. Potentially affects S and/or Z if AP or APC is the destination.

Note 4: The ‘{L/S}’ prefix is optional.

Note 5: Instructions that attempt to simultaneously push/pop the stack (e.g., PUSH @SP--, PUSH @SPI--, POP @++SP, POPI

@++SP) or modify SP in a conflicting manner (e.g., MOVE SP, @SP--) are invalid.

Note 6: The enabled AP autoincrement or decrement operation occurs for operations when specifying the active accumulator

(Acc) as the source or destination (i.e., MOVE Acc, src; MOVE dst, Acc; MOVE Acc, Acc). Special cases: If ‘MOVE APC,

Acc’ sets the APC.CLR bit, AP is cleared, overriding any autoinc/dec/modulo operation specified for AP. If ‘MOVE AP,

Acc’ causes an autoinc/dec/modulo operation on AP, this overrides the specified data transfer (i.e., Acc is not trans-

ferred to AP).

Note 7: Exception for MOVE instruction, MOVE dp, @cp requires three cycles.

Note 8: The terms Acc and A[AP] can be used interchangeably to denote the active accumulator.

Note 9: Any index represented by <b> or found inside [ ] brackets is considered variable, but required.

Note 10: The active accumulator (Acc) is not allowed as the dst if A[AP] is specified as the src.

MNEMONIC DESCRIPTION

16-BIT INSTRUCTION

WORD

STATUS

BITS

AFFECTED

INC/DEC

EXECUTION

CYCLES

NOTES

BRANCHING

{L/S}JUMP src

IP ← IP + src or src

f000 1100 ssss ssss — — 2 4

{L/S}JUMP C, src

If C=1, IP ← (IP + src) or src

f010 1100 ssss ssss — — 2 4

{L/S}JUMP NC, src

If C=0, IP ← (IP + src) or src

f110 1100 ssss ssss — — 2 4

{L/S}JUMP Z, src

If Z=1, IP ← (IP + src) or src

f001 1100 ssss ssss — — 2 4

{L/S}JUMP NZ, src

If Z=0, IP ← (IP + src) or src

f101 1100 ssss ssss — — 2 4

{L/S}JUMP E, src

If E=1, IP ← (IP + src) or src

0011 1100 ssss ssss — — 2 4

{L/S}JUMP NE, src

If E=0, IP ← (IP + src) or src

0111 1100 ssss ssss — — 2 4

{L/S}JUMP S, src

If S=1, IP ← (IP + src) or src

f100 1100 ssss ssss — — 2 4

{L/S}DJNZ LC[n], src

If --LC[n] <> 0, IP← (IP + src) or src

f10n 1101 ssss ssss — — 2 4

{L/S}CALL src

@++SP ← IP+1; IP ← (IP+src) or src

f011 1101 ssss ssss — — 2 4, 5

RET

IP ← @SP--

1000 1100 0000 1101 — — 2 —

RET C

If C=1, IP ← @SP--

1010 1100 0000 1101 — — 2 —

RET NC

If C=0, IP ← @SP--

1110 1100 0000 1101 — — 2 —

RET Z

If Z=1, IP ← @SP--

1001 1100 0000 1101 — — 2 —

RET NZ

If Z=0, IP ← @SP--

1101 1100 0000 1101 — — 2 —

RET S

If S=1, IP ← @SP--

1100 1100 0000 1101 — — 2 —

RETI

IP ← @SP-- ; IPS←11b

1000 1100 1000 1101 — — 2 —

RETI C

If C=1, IP ← @SP-- ; IPS←11b

1010 1100 1000 1101 — — 2 —

RETI NC

If C=0, IP ← @SP-- ; IPS←11b

1110 1100 1000 1101 — — 2 —

RETI Z

If Z=1, IP ← @SP-- ; IPS←11b

1001 1100 1000 1101 — — 2 —

RETI NZ

If Z=0, IP ← @SP-- ; IPS←11b

1101 1100 1000 1101 — — 2 —

RETI S

If S=1, IP ← @SP-- ; IPS←11b

1100 1100 1000 1101 — — 2 —

DATA

TRANSFER

XCH Swap Acc bytes 1000 1010 1000 1010 S Y 1 —

XCHN Swap nibbles in each Acc byte 1000 1010 0111 1010 S Y 1 —

MOVE dst, src

dst ← src

fddd dddd ssss ssss C, S, Z, E (Note 6) (Notes 2, 7) 5, 6

PUSH src

@++SP ← src

f000 1101 ssss ssss — — (Note 2) 5

POP dst

dst ← @SP--

1ddd dddd 0000 1101 C, S, Z, E — (Note 2) 5

POPI dst

dst ← @SP-- ; IPS←11b

1ddd dddd 1000 1101 C, S, Z, E — (Note 2) 5

CMP src

E ← (Acc = src)

f111 1000 ssss ssss E — 1 —

NOP No operation 1101 1010 0011 1010 — — 1 —

1 2 ... 207 208 209 210 211 212 213 214 215 216 217 ... 254 255

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