Maxim-integrated MAXQ622 Manual do Utilizador Página 112

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MAXQ612/MAXQ622 Users Guide
6-10 Maxim Integrated
6.2 External Interrupt Register Descriptions
Each bit in this register is set when a negative edge or a positive edge (depending on the ITn bit setting) is detected
on the corresponding interrupt pin. Once an external interrupt has been detected, the interrupt flag bit will remain
set until cleared by software or a reset. Setting any of these bits causes the corresponding interrupt to trigger if it is
enabled to do so.
Bit 7: External Interrupt 7 Edge Detect (IE7)
Bit 6: External Interrupt 6 Edge Detect (IE6)
Bit 5: External Interrupt 5 Edge Detect (IE5)
Bit 4: External Interrupt 4 Edge Detect (IE4)
Bit 3: External Interrupt 3 Edge Detect (IE3)
Bit 2: External Interrupt 2 Edge Detect (IE2)
Bit 1: External Interrupt 1 Edge Detect (IE1)
Bit 0: External Interrupt 0 Edge Detect (IE0)
Each bit in this register is set when a negative edge or a positive edge (depending on the ITn bit setting) is detected
on the corresponding interrupt pin. Once an external interrupt has been detected, the interrupt flag bit remains set until
cleared by software or a reset. Setting any of these bits causes the corresponding interrupt to trigger if it is enabled
to do so.
Bit 7: External Interrupt 15 Edge Detect (IE15)
Bit 6: External Interrupt 14 Edge Detect (IE14)
Bit 5: External Interrupt 13 Edge Detect (IE13)
Bit 4: External Interrupt 12 Edge Detect (IE12)
Bit 3: External Interrupt 11 Edge Detect (IE11)
Bit 2: External Interrupt 10 Edge Detect (IE10)
Bit 1: External Interrupt 9 Edge Detect (IE9)
Bit 0: External Interrupt 8 Edge Detect (IE8)
Register Name
EIF1
Register Description
External Interrupt Flag 1 Register
Register Address
M0[07h]
Bit # 7 6 5 4 3 2 1 0
Name IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Register Name
EIF0
Register Description
External Interrupt Flag 0 Register
Register Address
M0[06h]
Bit # 7 6 5 4 3 2 1 0
Name IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
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