Maxim-integrated MAXQ622 Manual do Utilizador descarregar pdf (Página 142)

MAXQ612/MAXQ622 User’s Guide

9-6 Maxim Integrated

Data is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples. Mode 2 uses

the sample divide-by-16 counter with either the clock divided by 2 or 4, thus resulting in a baud clock of either system

clock/32 or system clock/64.

Figure 9-3. USART Mode 2

DIVIDE

BY 2

LOAD

CLOCK

TRANSMIT SHIFT REGISTER

LATCH

RECEIVE DATA BUFFER WR

SBUF

CLOCK

RECEIVE SHIFT REGISTER

RESET

SHIFT

CLOCK

LOAD

SERIAL

BUFFER

LOAD

SERIAL I/O

CONTROL

INTS

SHIFT

READ

SERIAL

BUFFER

FLAG =

SCON.1

FLAG =

SCON.0

DIVIDE

BY 16

LDSBUF

RDSBUF

0 1

SBUF

SMOD

RXD

SYSTEM

CLOCK/2

DIVIDE

BY 16

BIT

DETECTION

TXD

RB8 =

SCON.2

TB8 =

SCON.3

START

STOP

START

STOP

SERIAL

INTERRUPT

DATA BUS

D0START

START

D1 D2 D3 D4 D5 D6 D7 RB8 STOP

D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP

RECEIVE TIMING

SHIFT

RXD

BIT DETECTOR

SAMPLING

TRANSMIT TIMING

LDSBUF

SHIFT

TXD

1 2 ... 137 138 139 140 141 142 143 144 145 146 147 ... 254 255

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