Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 134)

___________________________________________________________________________________________________________ 8-4

MAXQ7667 User’s Guide

Figur

e 8-1. UART/LIN Block Diagram

MAXQ

CORE

NTERRUPTS

SBUF

RANSMIT REGISTER

BREAK/SYNC

GENERATOR

LIN PROTOCOL

STATE MACHINES

LIN CONTROL

REGISTERS

CHECKSUM

PARITY

Tx FIFO

FILTER/RECEIVE

BAUD-RATE

GENERATOR

Tx PIN

Rx PIN

Rx FIFO

SECTION 8: UART AND LIN

The MAXQ7667 contains a standard UART for serial communication and dedicated hardware for support of the LIN bus. The dedicat-

ed LIN hardware simplifies the application code and requires less processor intervention. The MAXQ7667 can be configured to use

either the UART or LIN. Both the UART and LIN require external bus transceivers to connect to the physical layer.

8.1 Architecture

Figure 8-1 shows the various blocks that comprise the UART/LIN interface. The interface to the UART/LIN hardware is accessed

hrough the MAXQ7667 core. The MAXQ7667 memory-mapped registers for the UART/LIN are found in Module 3 of the peripheral reg-

ister map.

8.2 UART/LIN Pins

The UART/LIN pins are multiplexed with GPIO port 0 pins.

Table 8-1. GPIO Port 0 UART/LIN Pins

PORT P0

SIGNA LS

PORT 0 PIN FUN CTION

P0.0/URX 9 Port 0, Bit 0, General - Purpose D ig ital I/O Bit. Alternately, it is used for U ART/LIN receive data.

P0.1/UTX 10 Port 0, Bit 1, General - Purpose D igital I/O Bit. Alternately, it is used for U ART/LIN transm it data.

1 2 ... 129 130 131 132 133 134 135 136 137 138 139 ... 346 347

Sem comentários

Maxim-integrated MAXQ7667 Manual do Utilizador Página 134