
___________________________________________________________________________________________________________ 6-4
MAXQ7667 User’s Guide
The input and output conditioning in Figure 6-1 is deter
mined by the status/control registers T2CNAx (Type 2 timer/counter control reg-
ister A), T2CNBx (Type 2 timer/counter control register B), and T2CFGx (Type 2 timer configuration register). See Section 6.2: Type 2
Timer/Counter Peripheral Registers for a detailed discussion of these registers.
T2Vx REGISTER
16-BIT UP COUNTER
T2Rx REGISTER
16-BIT RELOAD
C
APTURE
EQUAL
OVERFLOW
RELOAD
CLOCK
T
2Cx REGISTER
1
6-BIT CAPTURE/COMPARE
OUTPUT CONDITIONING
POLARITY SELECTION
INPUT CONDITIONING
SCALING
GATING
Figure 6-1. Type 2 Timer/Counter in 16-Bit Mode
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