_________________________________________________________________________________________________________ 13-12
MAXQ7667 User’s Guide
Table 13-4. JTAG Status Decode
BITS (1:0) STAT US CON D ITION
0 0 Reser v ed Inva li d condi t ion.
0 1 Reser v ed Inva li d condi t ion.
1 0 Loader - Busy
RO M loade r is busy execut ing co de o r
p r oces s in g the cur rent com mand.
1 1 Loader - V a li d
RO M loade r is supp l yi ng v al i d out put data to
the host in curr ent sh ift ope rat ion.
• SPB.2 and SPB.1: Programming Source Select (PSS[1:0]). These bits allow the host to select programming interface sources.
PSS[1:0] = 00 for JTAG; PSS[1:0] = 01 for UART.
The DR-scan sequence is used to configure the SPB bits. The data content of the SPB register is reflected in the ICDF register and
allows read/write access by the CPU. These bits are cleared by power-on reset or test-logic-reset of the TAP controller.
The MAXQ7667 JTAG bootloader uses the same status bit handshaking hardware as is used for in-circuit debugging. When the SPE
bit of the system programming buffer (SPB) is set to 1 and JTAG is selected as the programming source (PSS[1:0] = 00b), the back-
ground and active-debug-mode state machines are disabled. Once the host loads the debug instruction into the TAP instruction reg-
ister (IR[2:0]), the 10-bit shift register interfaces to ICDB and the status bits become available for JTAG-to-ROM bootloader communi-
cation. The status bits should be interpreted as noted in Table 13-4 for a JTAG bootloader operation.
When the using the JTAG bootloader option (SPE = 1, PSS[1:0] = 00b), the sole purpose of the debug hardware is to simultaneously
transfer the data byte shifted in from the host into the ICDB register and transfer the contents of an internal holding register (loaded by
ROM code writes of ICDB) into the shift register for output to the host. This transfer takes place on the falling edge of TCK at the update-
DR state. The debug hardware additionally clears the TXC bit at this point in the state diagram. The ROM-loader code controls the sta-
tus bit output to the host by asserting TXC = 1 when it has valid data to be shifted out. The ROM code can flexibly implement what-
ever communication protocol and command set it wishes within the data byte portion of the shifted 10-bit word.
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