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12-7 __________________________________________________________________________________________________________

MAXQ7667 User’s Guide

12.2.4 In-Circuit Debug Flag Register (ICDF)

Bits 7 to 4: Reserved.

Read 0, write ignored.

Bits 3 and 2: Programming Source Select Bits 1 and 0 (PSS[1:0]). See Section 13 for information on these bits.

Bit 1: System Program Enable (SPE). See Section 13 for information on this bit.

Bit 0: Serial Transfer Enable (TXC). This bit is set by hardware at the end of a transfer cycle at the TAP communication link. The TXC

bit helps the debug engine to recognize host requests, either command or data. This bit is normally set by ROM code to signify or

request the sending or receiving of data. Once set, the debug engine clears the TXC bit. CPU writes to the TXC bit result in the clear-

ing of the JTAG PSS[1:0] bits.

12.2.5 In-Circuit Debug Buffer Register (ICDB)

The ICDB register serves as the parallel holding buffer for the debug shift register of the TAP. Data is read from or written to ICDB for

serial communication between the debug routines and the external host. This register is cleared to 00h after a power-on reset or a test-

logic-reset TAP state.

In-Circuit Debug Buffer Register

Bits 7 to 0: In-Circuit Debug Buffer Register Bits 7:0 (ICDB[7:0])

Bit #

76543210

Name — — — — PSS1 PSS0 SPE TXC

Reset 0 0 0 0 0 0 0 0

Access r r r r rw rw rw rw

r = read, w = write

Bit #

76543210

Name ICDB7 ICDB6 ICDB5 ICDB4 ICDB3 ICDB2 ICDB1 ICDB0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw rw rw rw rw

r = read, w = write

1 2 ... 200 201 202 203 204 205 206 207 208 209 210 ... 346 347

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Maxim-integrated MAXQ7667 Manual do Utilizador Página 205