Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 240)

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__________________________________________________________________________________________________________ 14-8

MAXQ7667 User’s Guide

14.3.4 SAR ADC Output Data Register (SARD)

Bits 15 to 12: Reserved.

Read returns 0.

Bits 11 to 0: SAR ADC Output Data 11:0 (SARD[11:0])

14.3.5 Oscillator Control Register (OSCC)

Bits 15 to 4: Reserved.

Read returns 0.

Bits 3 and 2: SAR ADC Clock Divider (SARCD[1:0]). Determines the SAR ADC clock frequency, which is divided down from the clock

source selected by the XTRC (CKCN.7) bit.

00 divides by 2

01 divides by 4

Bit #

15 14 13 12 11 10 98

Name — — — — SARD11 SARD10 SARD9 SARD8

Reset 0 0 0 0 0 0 0 0

Access r r r r r r r r

Bit #

76543210

Name SARD7 SARD6 SARD5 SARD4 SARD3 SARD2 SARD1 SARD0

Reset 0 0 0 0 0 0 0 0

Access r r r r r r r r

r = read

Note: SARD is cleared to 0000h on all forms of reset.

Bit #

15 14 13 12 11 10 98

Name — — — — — — — —

Reset 0 0 0 0 0 0 0 0

Access r r r r r r r r

Bit #

76543210

Name — — — — SARCD1 SARCD0 XTE RCE

Reset 0 0 0 0 0 0 0 0

Access r r r r r r r r

r = read (Note that some clock control bits may have locking mechanisms for write.)

Note: OSCC is cleared to 0000h on power-on reset.

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