Maxim-integrated MAXQ7667 Manual do Utilizador Página 252

  • Descarregar
  • Adicionar aos meus manuais
  • Imprimir
  • Página
    / 347
  • Índice
  • MARCADORES
  • Avaliado. / 5. Com base em avaliações de clientes
Vista de página 251
_________________________________________________________________________________________________________ 14-20
MAXQ7667 Users Guide
Figure 14-11. Setting Up and Using the ADC Flow Chart
SELECT IN SAR ADC CONTROL REGISTER 
SARC:
A) DIFFERENTIAL OR SINGLE-ENDED
CONVERSION.
B) IF DIFFERENTIAL CONVERSION, 
SELECT UNIPOLAR OR BIPOLAR MODE.
C) SET SARASD IF ADC AUTO
SHUTDOWN IS REQUIRED.
D) SET SARRSEL TO EITHER SELECT
EXTERNAL/INTERNAL ADC REFERENCE
OR THE AVDD.
SELECT IN SARC REGISTER (CONT’d.): 
E) ADC CONVERSION START SOURCE:
TIMERS 0–2, ADCCTL PIN, SW WRITE
(START/BUSY BIT). 
F) SINGLE OR DUAL EDGE: FOR ADC
LOGIC-CONTROLLED ACQUISITION 
TIME, SELECT SINGLE EDGE (0); FOR 
USER-CONTROLLER ACQUISITION
TIME, SELECT DUAL EDGE (1). 
G) ADC INPUT CHANNEL.
START ADC CONVERSION:
DEPENDING ON ADC CONVERSION
START SOURCE SET TIMER ENABLE 
(PIN IS ALREADY INPUT), OR ADC START/
BUSY BIT IN SARC TO TRIGGER 
CONVERSION. 
NOTE: FOR CONTINUOUS MODE, 
SELECTING 110 IN SARS[2:0] FIELD 
TRIGGERS CONVERSION.
IF POLLED CONVERSION, WAIT FOR 
SARRDY BIT IN ADC STATUS REGISTER 
TO BE SET BEFORE READING THE ADC 
DATA REGISTER. OTHERWISE, READ 
ADC DATA AFTER ADC DATA READY 
INTERRUPT.
READ AND SAVE 12-BIT ADC RESULT 
(CODE
12
) FROM ADC DATA REGISTER, SARD.
SELECT ADC CLOCK DIVIDE SARCD[1:0] 
RATIO IN THE OSCC REGISTER.
SELECT IN ADC POWER ENABLE
REGISTER (APE):
A) SET SARE (APE.4) TO ENABLE ADC.
B) IF INTERNAL BANDGAP REFERENCE IS
DESIRED, SET BGE (APE.12).
C) SET RBUFE (APE.14) TO ENABLE ADC 
REFERENCE BUFFER.
IF CONVERSION START SOURCE IS
GOING TO BE ONE OF THE TIMERS, 
CONFIGURE TIMER IN 16-BIT OR 8-BIT
MODE. NOTE: TIMER OUTPUT IS
INTERNALLY SELECTED AS THE ADC START
TRIGGER CONTROL.
IF CONVERSION START SOURCE IS FROM
EXTERNAL ADCCTL PIN, ENSURE PIN IS
CONFIGURED AS INPUT.
TO GET ADC DATA READY INTERRUPT 
AFTER A CONVERSION, SET SARIE (AIE.0) 
BIT IN ANALOG INTERRUPT ENABLE 
REGISTER. ALSO, ENABLE MODULE AND 
GLOBAL INTERRUPT CONTROL BITS IM5 IN 
IMR AND IGE IN IC PERIPHERAL REGISTER.
Vista de página 251
1 2 ... 247 248 249 250 251 252 253 254 255 256 257 ... 346 347

Comentários a estes Manuais

Sem comentários