Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 207)

12-9 __________________________________________________________________________________________________________

MAXQ7667 User’s Guide

12.2.8 System Control Register (SC)

Bit 7: Test Access (JTAG) Port Enable (TAP).

This bit controls whether the TAP special function pins are enabled. The TAP defaults

to being enabled. See

Section 11 for more information on this bit.

0 = JTAG/TAP functions are disabled and P0.0–P0.3 can be used as general-purpose I/O pins

1 = TAP special function pins P0.0–P0.3 are enabled to act as JTAG inputs and outputs

Bits 6 and 0: Reserved

Bits 5 and 4: Code Data Access Bits 1 and 0 (CDA[1:0]). See Section 2 for more information on these bits.

Bit 3: Upper Program Access (UPA). See Section 2 for more information on this bit.

Bit 2: ROM Operation Done (ROD). This bit is used to signify completion of a ROM operation sequence. The utility ROM signals that

it has completed a requested task by setting the ROD (ROM operation done) bit of the SC register to logic 1. The ROD bit is reset by

the debug engine when it recognizes the done condition. Setting the ROD bit to 1 when the SPE bit is also set causes the system to

reset.

Bit 1: Password Lock (PWL). This bit defaults to 1 on a power-on reset. When this bit is 1, it requires a 32-byte password to be

matched with the password in the program space before allowing access to the password protected in-circuit debug or bootstrap

loader ROM routines. Clearing this bit to 0 disables the password protection for these ROM routines. See

Section 13 for more infor-

mation on this bit.

Bit #

76543210

Name TAP — CDA1 CDA0 UPA ROD PWL —

Reset 0 0 0 0 0 0 1 0

Access rw r rw rw rw rw rw r

r = read, w = write

*This register defaults to 80h on all forms of reset except after power-on reset. After power-on reset, the PWL bit is also set and this register defaults to 82h.

1 2 ... 202 203 204 205 206 207 208 209 210 211 212 ... 346 347

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