Maxim-integrated MAXQ7667 Manual do Utilizador Página 94

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5-19 __________________________________________________________________________________________________________
MAXQ7667 Users Guide
5.3.4 Port Pin Examples
5.3.4.1 Port Pin Example 1: Driving Outputs on Port 0
move PS0, #000h ; Set the output drive strength to 1 mA (approx)
move PO0, #000h ; Set all outputs low
move PD0, #0FFh ; Set all P0 pins to output mode
5.3.4.2 Port Pin Example 2: Receiving Inputs on Port 0
move PO0, #0FFh ; Set weak pullups ON on all pins
move PD0, #000h ; Set all P0 pins to input mode
nop ; Wait for external source to drive P1
move Acc, PI0 ; Get input values from P0
; (will return FF if no other source
; drives the pins low)
PORT P1
PIN
FU N CTION
TYPE
FU N CTION EN AB LED W HEN MU LTIPLEXING/PRIORITIZA TION
Special
SCLK—Serial C lock, Master
Mode, Output
Special
SCLK—Serial C lock,
Slave Mode, Input
P1.6/SCLK
Alternate External Inter rupt 6, Input (EIE1.6) E X6 = 1
This port pin is defaulted as a weak pullup
input after a reset. If interrupt 14 is enabled,
SCLK is not permi tted at this pin.
Special
SY NC—Resets the
Synchronous Timer
(S CN T.8) SSY NC_ E N = 1
Special
SS— Slave Select for the SPI,
Input, Slave Mode
(S PICN.0) SPIE N = 1
(S PICN.1) MST M = 0
(S PICN.2) MODFE = 0
Special
SS— Slave Select for the SPI,
Input, Master Mode
(S PICN.0) SPIE N = 1
(S PICN.1) MST M = 1
(S PICN.2) MODFE = 1
P1.7/SYN C/
SS
Alternate External Inter rupt 7, Input (EIE1.7) E X7 = 1
This port pin is defaulted as a w eak pullup
input after a reset. If the SPI is enabled as a
slave, this pin is the s lave select input. If the
synchronous ti mer has SS YN C_EN = 1, the
next ris ing edge on this pin causes a reset of
the synchronous ti mer 's count and the
clearing of SSY NC_ EN. Note that the ris ing
edge detection is perfor med by
synchronizing the input to the CP U clock
(after any clock div is ion), and as such a
high- going pulse must be greater than 2x
TCK to be detected.
Table 5-5. Port P1 Pin Special and Alternate Functions (continued)
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