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PORT P1
SIGNA LS
PIN FUN CTION
P1.0/TD0 46 D ig ital GPIO and JTAG Ser ial Data Output. As TDO this pin is the JTAG serial test data output.
P1.1/TMS 47 Di g ital GPIO and JTAG Test Mode Select Input. As TMS this p in is the JTAG test mode select input.
P1.2/TDI 48 Di g ital GPIO and JTAG. As TDI this p in is the JTAG serial test data input.
P1.3/TCK 1 D ig ital GPIO and JTAG Serial C lock Input. As TCK this p in is the JTAG serial test clock input.
P1.4/MOSI 2 D ig ital GPIO and SPI Ser ial Data I/O. As MOSI this pin is the master out-s lave in for the SPI interface.
P1.5/MISO 3 D ig ital GPIO and SPI Ser ial Data I/O. As MISO this pin is the master in-s lave out for the SPI interface.
P1.6/SCLK 4 D i g ital GPIO and SPI Ser ial C lock. As SCLK this pin is the serial clock for the SPI interface.
P1.7/SYN C/ SS 5 Di g ital GPIO, System Timer Sy nc Input, and SPI Port S lave Select. As SYNC this p in resets the system timer.
PORT P0
SIGNA LS
PIN FUN CTION
P0.0/URX 9
D ig ital GPIO and UART Receive Data Input. As URX this pin is the receive data input of the UART, which can
(optionally ) be connected to RXD of a LIN transceiver.
P0.1/UTX 10
D ig ital GPIO and UART Trans mit Data Output. As UTX this pin is the transm it data output of the UART, which can
(optionally ) be connected to TXD of a LIN transceiver.
P0.2/TXEN
11
D ig ital GPIO and UART Trans mit. As TXEN the pin can be used to control the trans mit enable of an external dr iv er. This
pin defaults to TXEN any ti me the UART is used. TXEN is high when the UART is receiving and low when the UART is
transmitting.
P0.3/T0/
ADC CTL
12
D ig ital GPIO, Ti mer 0 I/O, and ADC Control Input. As T0 this p in is the pr imary timer/PWM0 input or output. As
ADC CTL this user - p rogra mmab le r is ing or fall ing edge controls the SAR ADC s amp l ing instant and start of
conversion. O ptionally, the other edge can be used to enable the AD C and begin acquiring p r io r to sampl ing.
P0.4/T0B 13
D ig ital GPIO, Ti mer 0 I/O, and Comparator Output. As T0B this pin is the secondary timer/PW M1 input or output. As
C MPO this p in is the output of the dig ital comparator for the lowpass filter.
P0.5/T1 14 D i g ital GPIO and Timer 1 I/O. As T1 this pin is the pr ima ry ti mer/ PWM2 input or output.
P0.6/T2 15 D i g ital GPIO and Timer 2 I/O. As T2 this pin is the pr ima ry ti mer/ PWM2 input or output.
P0.7/T2B 16 Di g ital GPIO and Timer 2 I/O . As T2B this pin is the secondary timer/P WM2 input or output.
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