Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 239)

14-7 __________________________________________________________________________________________________________

MAXQ7667 User’s Guide

14.3.3 Analog Status Register (ASR)

Bit 15: DVDDIO Brownout Comparator Output Level (VIOLVL).

See Section 16 for details on this bit.

Bit 14: DVDD Brownout Comparator Output Level (DVLVL). See Section 16 for details on this bit.

Bit 13: AVDD Brownout Comparator Output Level (AVLVL). See Section 16 for details on this bit.

Bit 12: Echo Envelope Comparator Output Level (CMPLVL). See Section 17 for details on this bit.

Bits 11 to 9: Reserved. Read returns 0.

Bit 8: Crystal Oscillator Ready (XTRDY). See Section 15 for details on this bit.

Bit 7: Crystal Oscillator Failure Interrupt Flag (XTI). See Section 15 for details on this bit.

Bit 6: DVDDIO Brownout Interrupt Flag (VIBI). See Section 16 for details on this bit.

Bit 5: DVDD Brownout Interrupt Flag (VDBI). See Section 16 for details on this bit.

Bit 4: AVDD Brownout Interrupt Flag (VABI). See Section 16 for details on this bit.

Bit 3: Echo Envelope Comparator Interrupt Flag (CMPI). See Section 17 for details on this bit.

Bit 2: Echo Envelope Lowpass Filter FIFO Full Interrupt Flag (LPFFL). See Section 17 for details on this bit.

Bit 1: Echo Envelope Lowpass Filter Output Data Ready Flag (LPFRDY). See Section 17 for details on this bit.

Bit 0: SAR ADC Data Ready Flag (SARRDY). Set to 1 when the SAR ADC completes a conversion.

Bit #

15 14 13 12 11 10 98

Name VIOLVL DVLVL AVLVL CMPLVL — — — XTRDY

Reset 0 0 0 0 0 0 0 0

Access r r r r r r r r

Bit #

76543210

Name XTI VIBI VDBI VABI CMPI LPFFL LPFRDY SARRDY

Reset 0 0 0 0 0 0 0 0

Access r r r r r r r r

r = read

Note: ASR bits 3:0 are cleared to 0h on reset; bits 8:4 clear to 0h on power-on reset.

1 2 ... 234 235 236 237 238 239 240 241 242 243 244 ... 346 347

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Maxim-integrated MAXQ7667 Manual do Utilizador Página 239