16.2.3 Analog Power Enable Register (APE)
Register Description: Analog Power Enable Register
Register Name: APE
Register Address: Module 05h, Index 10h
Bits 15 and 13: Reserved.
Read returns 0.
Bit 14: Reference Buffer Enable (RBUFE). Set to 1 to enable; set to 0 to disable.
Bit 12: Bandgap Enable (BGE). Set to 1 to enable; set to 0 to disable.
Bit 11: I/O Linear Regulator Power-Down (LRIOPD). When set to 1, this bit disables the DVDDIO linear regulator and places the
GATE5 pin into high-impedance mode. When set to 0, this bit powers up the regulator.
Bit 10: Digital Linear Regulator Power-Down (LRDPD). When set to 1, this bit disables the DVDD linear regulator and places it in a
leakage-only state. When set to 0, this bit powers up the regulator.
Bit 9: Analog Linear Regulator Power-Down (LRAPD). When set to 1, this bit disables the AVDD linear regulator and places it in a
leakage-only state. When set to 0, this bit powers up the regulator.
Bit 8: I/O Voltage Brownout Detection Enable (VIBE). When set to 1, this bit enables the DVDDIO monitor to generate an interrupt if
the VIBIE bit is also set and DVDDIO falls below the specified threshold. When set to 0, this bit disables the DVDDIO monitor and places
it in a leakage-only state.
Bit 7: Digital Voltage Reset Enable (VDPE). When set to 0, this bit disables the DVDD reset supervisor. This bit defaults to 1 at reset.
Bit 6: Digital Voltage Brownout Detection Enable (VDBE). When set to 1, this bit enables the DVDD monitor to generate an interrupt
if the VDBIE bit is also set and DVDD falls below the specified threshold. When set to 0, this bit disables the DVDD monitor and places
it in a leakage-only state.
Bit 5: Analog Voltage Brownout Detection Enable (VABE). When set to 1, this bit enables the AVDD monitor to generate an interrupt
if the VABIE bit is also set and AVDD falls below the specified threshold. When set to 0, this bit disables the AVDD monitor and places
it in a leakage-only state.
Bit 4: SAR Enable (SARE). See Section 14 for details on this bit.
Bit 3: PLL Enable (PLLE). See Section 17 for details on this bit.
Bit 2: Sigma-Delta Modulator Enable (MDE). See Section 17 for details on this bit.
Bit 1: LNA Enable (LNAE). See Section 17 for more information on this bit.
Bit 0: Bias Enable (BIASE). See Section 14 and Section 17 for more information on this bit.
16-7 __________________________________________________________________________________________________________
MAXQ7667 User’s Guide
r = read, w = write
Note: APE is cleared to 0080h on all forms of reset.
Bit #
15 14 13 12 11 10 98
Name — RBUFE — BGE LRIOPD LRDPD LRAPD VIBE
Reset 0 0 0 0 0 0 0 0
Access r rw r rw rw rw rw rw
Bit #
76543210
Name VDPE VDBE VABE SARE PLLE MDE LNAE BIASE
Reset 1 0 0 0 0 0 0 0
Access rw rw rw r rw rw rw rw
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