Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 265)

As shown in Figure 15-2, the timer is driven by the internal RC clock (set at the maximum 16MHz frequency) through a series of

dividers. The divider output is selectable and determines the interval between timeouts. When the watchdog interrupt timeout is

eached, the interrupt flag WDIF (WDCN.3) is set and generates an interrupt if the interrupt enable bit EWDI (WDCN.6) bit is set.

Typically, after the WDIF gets set the user code resets the watchdog timer RWT (WDCN.0). In the case when this bit is not cleared

before the watchdog reset timeout, the MAXQ7667 undergoes a soft reset.

he watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. At normal clock frequency, the

interrupt timeout has a default divide ratio of 2

the source clock, with the watchdog reset set to time out 2

clock cycles later. This

results in a 16MHz internal RC clock producing an interrupt timeout every 0.256ms (2

/16MHz), followed by a watchdog reset, 32.0µs

/16MHz) later. The watchdog timer is reset to the default divide ratio (2

) following any reset. Using the WD0 and WD1 bits in the

WDCN register, other divide ratios can be selected for longer watchdog interrupt periods. If the WD[1:0] bits are changed before the

watchdog interrupt timeout occurs (i.e., before the watchdog reset counter begins), the watchdog timer count is reset. All watchdog

timer reset timeouts follow the programmed interrupt timeouts by 512 (or 2

) times the divider ratio of the source clock cycles. Table

15-3 summarizes the watchdog bit settings and the timeout values.

Table 15-3. Watchdog Timeout Values (in Number of Source Clock Cycles)

15.6 Oscillator/Clock Power-Saving Management Modes

15.6.1 Stop Mode

The stop mode disables all circuits within the processor. All on-chip clocks, timers, and serial port communication are stopped, and no

processing is possible. Once in stop mode, the device is in a static state; its power consumption is mostly limited by the leakage current.

Stop mode is invoked by setting the STOP bit (CKCN.4) to logic 1. The processor enters stop mode on the instruction that sets the

STOP bit. Entering stop mode does not affect the setting of the clock control bits; this allows the system to return to its original oper-

ating frequency following the stop mode removal.

The processor can exit the stop mode:

• By using any of the external interrupts that are enabled

• By external reset via the

RESET pin

When the stop mode is removed, the processor resumes its normal execution:

• After a four-cycle delay:

If XTRC is 1, the RC oscillator is used until XTRDY is set to logic 1 (indicating external clock is stable) before switching back

to exter

nal clock sour

ce.

If XTRC is 0, the inter

nal RC oscillator is the clock sour

ce.

15.6.1.1 Resuming from Stop Mode

When the system is in stop mode while the system clock is sour

ced fr

om the exter

nal high-frequency source, the internal RC oscilla-

tor is disabled. When stop mode is removed, the crystal oscillator requires a long period of time to start up and stabilize. To allow the

system to begin quick execution of software following the removal of stop mode, the RC oscillator can be used to supply a system

clock until the cr

ystal star

tup time is satisfied. Once this time has passed, the inter

nal system clock is switched over to the exter

nal

ystal oscillator

. T

o allow the processor to know when it is being clocked by the RC oscillator or the crystal oscillator, the RCMD bit

indicates which clock source is being used.

15-13 _________________________________________________________________________________________________________

MAXQ7667 User’s Guide

WD[1:0] DIVIDE RATIO

WAT C H D OG INTERR UPT TI MEOUT = DIVIDE

R A TIO/16MHz

(ms)

WAT C H D OG RESET TIMEOUT = DIVIDE

R A TIO/16MHz + 2

/16MHz

(ms)

00 (default)

0.256 0.256 + 0.032

2.048 2.048 + 0.032

16.384 16.384 + 0.032

131.072 131.072 + 0.032

1 2 ... 260 261 262 263 264 265 266 267 268 269 270 ... 346 347

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