Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 58)

__________________________________________________________________________________________________________ 4-14

MAXQ7667 User’s Guide

4.1.14 Interrupt Vector Register (IV)

Bits 15 to 0: Interrupt Vector Register Bits 15:0 (IV[15:0]).

This register contains the address of the interrupt service routine. The

interrupt handler will generate a CALL to this address whenever an interrupt is acknowledged.

4.1.15 Loop Counter 0 Register (LC[0])

Bits 15 to 0: Loop Counter 0 Register Bits 15:0 (LC[0][15:0])

. This register is used as the loop counter for the DJNZ LC[0], src oper-

ation. This operation decrements LC[0] by one and then jumps to the address specified in the instruction by src.

Bit #

15 14 13 12 11 10 9 8

Name IV15 IV14 IV13 IV12 IV11 IV10 IV9 IV8

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

Bit #

7 6543210

Name IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

r = read, w = write

Note: This register is cleared to 0000h on all forms of reset.

Bit #

15 14 13 12 11 10 9 8

Name LC[0]15 LC[0]14 LC[0]13 LC[0]12 LC[0]11 LC[0]10 LC[0]9 LC[0]8

Reset 0 0 0 0 0 0 0 0

Access r w r w r w r w r w r w r w r w

Bit #

76543210

Name LC[0]7 LC[0]6 LC[0]5 LC[0]4 LC[0]3 LC[0]2 LC[0]1 LC[0]0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

r = read, w = write

Note: This register is cleared to 0000h on all forms of reset.

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Maxim-integrated MAXQ7667 Manual do Utilizador Página 58