9-5 ___________________________________________________________________________________________________________
MAXQ7667 User’s Guide
The MAXQ7667 supports:
• 8-bit or 16-bit character lengths
• Master or slave mode
• Four standard SPI clocking modes
• Programmable master SPICK baud-rate generator
• Configurable SS pin
• MSB first data shifting
• Mode-fault detection
• Data overrun and collision detection
• Interrupt or polled operation
The MAXQ7667 does not support:
• Free-running SPICK and frame sync transfer modes
• LSB first shift
Peripherals used should be compatible with the MAXQ7667-supported SPI modes.
Table 9-1. SPI Port I/O Pins
Additional SS pins in master mode can be defined under firmware control using the digital I/O pins.
9.1.1 SPI Status and Control Registers
Four registers control the SPI port configuration, report status, and operation in the MAXQ7667. These registers are found in the spe-
cial function register bank in Module 1, indexes 6, 7, 8, and 9. The registers are:
• SPI Data Buffer Register (SPIB): Module 1, Index 6
• SPI Control Register (SPICN): Module 1, Index 7
• SPI Configuration Register (SPICF): Module 1, Index 8
• SPI Clock Register (SPICK): Module 1, Index 9
PIN
MU L TIPLEXED
WIT H POR T
PIN
INTERF ACE
SIGNA L
FUN CTION
3 P1.5 MISO
Ma ste r In- S l ave Out. This si g nal is an output fro m an SPI s lave dev ice and an input fo r an S PI m a ste r
device. It i s used to s erial l y t ransfer data f ro m the slave to the maste r. Data is tr ansfer r e d MS B f i r s t.
2 P1.4 MO SI
Ma ste r Out- S la ve In. This s i g nal is an output fro m an SPI ma s ter dev i ce and an in put for an SP I s lave
device. It i s used to s erial l y t ransfer data f ro m a maste r to a slave dev ice. D ata is t ransfer r e d MS B
fi r st. When in slave mode, the M A XQ default confi gur at ion fo r MI S O i s an input w i th a weak pul lup .
4 P1.6 SCLK
SP I C l ock. Th is se r ia l clock is an out put f ro m an S PI ma ste r device and an input for an S PI sla ve
device. It i s used to s h ift the data between a mas ter and a s lave device. The c lock polari t y s elect
(C K POL ) and the c lock phas e select ( CK P H A ) b i ts confi gu re the S C LK mode used. The MA XQ7667
su p por ts a l l four S P I clock ing mo des.
5 P1.7 SS
Sl a ve Select. The slave - se lect s i gnal can be confi gure d (S P I CF r eg i ste r ) as an act ive - l ow o r act iv e -
hi gh input. In the s lave mo de, S S i s asse r ted and hel d low o r hi gh ( based on its conf igu ration) fo r the
entire t ransfer. Shi ftin g out, or in, i s sto p ped when S S is deass erte d. Th is p in can a lso be conf igu re d
to detect a mode - fault condi t ion in maste r m o de.
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