Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 51)

4-7 ___________________________________________________________________________________________________________

MAXQ7667 User’s Guide

Bits 2 to 0: Accumulator Pointer Autoincrement/Decrement Modulus (MOD[2:0]). If these bits are set to a nonzero value, the accu-

mulator pointer (AP[3:0]) will be automatically incremented or decremented following each arithmetic or logical operation. The mode

for the autoincrement/decrement is determined as follows:

4.1.3 Processor Status Flags Register (PSF)

Bit 7: Zero Flag (Z).

The value of this bit flag equals 1 whenever the active accumulator is equal to zero, and it equals 0 otherwise.

Bit 6: Sign Flag (S). This bit flag mirrors the current value of the high bit of the active accumulator (Acc.15).

Bit 5: Reserved. Read 0, write ignored.

Bits 4 and 3: General-Purpose Software Flag 1 and 0 (GPF[1:0]). These general-purpose register bits are provided for user software

control.

Bit 2: Overflow Flag (OV). This flag is set to 1 if there is a carry out of bit 14 but not out of bit 15, or a carry out of bit 15 but not out

of bit 14 from the last arithmetic operation, otherwise, the OV flag remains as 0. OV indicates a negative number resulted as the sum

of two positive operands, or a positive sum resulted from two negative operands.

Bit 1: Carry Flag (C). This bit flag is set to 1 whenever an add or subtract operation (ADD, ADDC, SUB, SUBB) returns a carry or bor-

row. This bit flag is cleared to 0 whenever an add or subtract operation does not return a carry or borrow. Many other instructions poten-

tially affect the carry bit. See

Section 19: Instruction Set Summary for details.

Bit 0: Equals Flag (E). This bit flag is set to 1 whenever a compare operation (CMP) returns an equal result. If a CMP operation returns

not equal, this bit is cleared.

MOD[2 :0] AU TOINCRE MEN T/DEC RE MEN T MODE

000 No autoincrement/decrement (default).

001 Increment/decrement AP[0] modulo 2.

010 Increment/decrement AP[1:0] modulo 4.

011 Increment/decrement AP[2:0] modulo 8.

100 Increment/decrement AP modulo 16.

101 to 111 Reserved (modulo 16 when set).

Bit #

76543210

Name Z S — GPF1 GPF0 OV CE

Reset 1 0 0 0 0 0 0 0

Access r r r rw rw r rw rw

r = read, w = write

Note: This register is cleared to 80h on all forms of reset.

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 346 347

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