Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 293)

17.3.6 Echo Envelope Comparator Control Register (CMPC)

Bit 15: Comparator Output Polarity (CMPP).

Set CMPP = 0 to generate an interrupt on the rising edge of the CMPLVL signal. Set

CMPP = 1 to generate an interrupt on the falling edge of the CMPLVL signal.

Bits 14 to 0: Comparator Hysteresis (CMPH[14:0]). This register holds the user-adjustable comparator hysteresis. CMPLVL is reset

to 0 when LPFD is less than CMPT minus CMPH.

17.3.7 Echo Envelope Comparator Threshold Register (CMPT)

Bits 15 to 0: Comparator Threshold (CMPT[15:0]).

This register holds the comparator threshold. CMPLVL is set to 1 when LPFD

exceeds CMPT.

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MAXQ7667 User’s Guide

r = read, w = write

Note: CMPC is cleared to 0000h on all forms of reset.

Bit #

15 14 13 12 11 10 98

Name CMPP CMPH14 CMPH13 CM PH12 CMP H11 CM PH10 CMPH9 CMPH8

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

Bit #

76543210

Name CM PH7 CMPH6 CMPH5 CMPH4 CMPH3 CMPH2 CMPH1 CMPH0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

r = read, w = write

Note: CMPT is cleared to 0000h on all forms of reset.

Bit #

15 14 13 12 11 10 98

Name CMPT15 CMPT14 CMPT13 CMPT12 CMPT11 CMPT10 CMPT9 CMPT8

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

Bit #

76543210

Name CMPT7 CMPT6 CMPT5 CMPT4 CMPT3 CMPT2 CMPT1 CMPT0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

1 2 ... 288 289 290 291 292 293 294 295 296 297 298 ... 346 347

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Maxim-integrated MAXQ7667 Manual do Utilizador Página 293