Maxim-integrated MAXQ7667 Manual do Utilizador descarregar pdf (Página 147)

100

101

8.3.17 Timer Register (UART) (TMR)

egister Name:

Bits 15 to 0: Timer Register 15:0 (TMR[15:0]).

This register is written by the host during system initialization to indicate the number

of system clock cycles in a 50µs period.

8.4 MAXQ7667 LIN

8.4.1 MAXQ7667 LIN Features

The MAXQ7667 LIN provides the following features:

• Supports LIN 1.3, LIN 2.0, and SAE J2602

• Automatic baud-rate detection and LIN frame synchronization

• Automatic calculation of standard (LIN 1.3) and enhanced (LIN 2.0) checksums

• Frame lengths up to 64 bytes

• Support for LIN power management modes

•

8-byte transmit and receive FIFOs to r

educe processor intervention

• Configurable digital filter for receiver

8-17 __________________________________________________________________________________________________________

MAXQ7667 User’s Guide

r = read, w = write

Note: TMR is cleared to 0000h on all forms of reset.

it #

5 14 13 12 11 10 98

Name TMR15 TMR14 TMR13 TMR12 TMR11 TMR10 TMR9 TMR8

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

Bit #

76543210

Name TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw r w rw rw rw

1 2 ... 142 143 144 145 146 147 148 149 150 151 152 ... 346 347

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