8.3.8 Status Register 0 (UART) (STA0)
Register Description: Status Register 0
R
egister Name:
S
TA0
Register Address: Module 03h, Index 11h
Bits 7 to 2: Reserved.
Bit 1: Interrupt Pending (INP).
This bit is set to 1 by the peripheral in LIN master or LIN slave mode when an interrupt condition occurs.
Bit 0: State Machine Busy (BUSY). This bit is set to 1 by the peripheral in LIN master or LIN slave mode when the state machine is
actively communicating on the bus.
8.3.9 Serial Mode Register (UART) (SMD)
Register Description: Serial Mode Register
Register Name: SMD
Register Address: Module 03h, Index 12h
Bit 7: Enable Infrared Modulation (EIR).
Setting this bit to 1 enables the peripheral to modulate the transmitted data with the wave-
for
m supplied by an on-chip timer. If this bit is clear
ed to 0, the infrar
ed modulation is disabled.
If the CONFIG_IR parameter is set to 0, this bit is not implemented and always reads 0.
Bit 6: Output Format Select (OFS). This bit determines the polarity of the output waveform when infrared modulation is enabled. If
OFS = 1, the modulated waveform is normally high. If OFS = 0, the modulated waveform is normally low.
If the CONFIG_IR parameter is set to 0, this bit is not implemented and always reads 0.
Bits 5 to 3: Reserved. Read retur
ns 0.
Bit 2: Serial Port Interrupt Enable (IE). Setting this bit to 1 enables the peripheral to issue interrupts. No interrupts are issued if this
bit is cleared to 0.
Bit 1: Serial Port Baud Rate Select (SMOD). In legacy UART mode, this bit enables a pr
escalar for the baud-rate generator. This bit
serves no purpose in LIN master or LIN slave mode. The SMOD selects the final baud rate for the asynchronous mode:
SMOD = 1: 16 times the baud clock for mode 1 and 3
32 times the system clock for mode 2
SMOD = 0:
64 times the baud clock for mode 1 and 3
64 times the system clock for mode 2
Bit 0: Framing Error Detection Enable (FEDE). Setting this bit to 1 enables access to the framing er
r
or detection flag thr
ough the
SM0 bit (SCON.7).
8-11 __________________________________________________________________________________________________________
MAXQ7667 User’s Guide
r = read
Note: STA0 is cleared to 00h on all forms of reset.
Bit #
76543210
Name — — — — — — INP BUSY
R
eset 0 0 0 0 0 0 0 0
A
ccess r r rrrrrr
r = read, w = write
Note: SMD is cleared to 00h on all forms of reset.
Bit #
76543210
Name EIR OFS — — — IE SMOD FEDE
Reset 0 0 0 0 0 0 0 0
Access rw rw rrrrw rw rw
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